fix fast-servo u-boot
This commit is contained in:
parent
62b8b691fe
commit
22129bc04e
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@ -1,694 +1,31 @@
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 480269fa60..92b06363dc 100644
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index 480269fa60..df94fc1213 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -334,6 +334,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
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@@ -333,6 +333,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
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uniphier-sld8-ref.dtb
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dtb-$(CONFIG_ARCH_ZYNQ) += \
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bitmain-antminer-s9.dtb \
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+ fast-servo.dtb \
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bitmain-antminer-s9.dtb \
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zynq-cc108.dtb \
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zynq-cse-nand.dtb \
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zynq-cse-nor.dtb \
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diff --git a/arch/arm/dts/fast-servo.dts b/arch/arm/dts/fast-servo.dts
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new file mode 100644
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index 0000000000..918d44a32c
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--- /dev/null
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+++ b/arch/arm/dts/fast-servo.dts
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@@ -0,0 +1,663 @@
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+# 0 "system-top.dts"
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+# 0 "<built-in>"
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+# 0 "<command-line>"
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+# 1 "system-top.dts"
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+
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+
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+
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+
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+
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+
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+
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+/dts-v1/;
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+# 1 "zynq-7000.dtsi" 1
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+# 15 "zynq-7000.dtsi"
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "xlnx,zynq-7000";
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ compatible = "arm,cortex-a9";
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+ device_type = "cpu";
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+ reg = <0>;
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+ clocks = <&clkc 3>;
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+ clock-latency = <1000>;
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+ cpu0-supply = <®ulator_vccpint>;
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+ operating-points = <
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+
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+ 666667 1000000
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+ 333334 1000000
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+ >;
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+ };
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+
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+ cpu1: cpu@1 {
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+ compatible = "arm,cortex-a9";
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+ device_type = "cpu";
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+ reg = <1>;
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+ clocks = <&clkc 3>;
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+ };
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+ };
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+
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+ fpga_full: fpga-full {
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+ compatible = "fpga-region";
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+ fpga-mgr = <&devcfg>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ };
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+
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+ pmu@f8891000 {
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+ compatible = "arm,cortex-a9-pmu";
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+ interrupts = <0 5 4>, <0 6 4>;
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+ interrupt-parent = <&intc>;
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+ reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
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+ };
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+
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+ regulator_vccpint: fixedregulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "VCCPINT";
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ replicator {
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+ compatible = "arm,coresight-static-replicator";
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+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+
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+ out-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+
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+ port@0 {
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+ reg = <0>;
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+ replicator_out_port0: endpoint {
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+ remote-endpoint = <&tpiu_in_port>;
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+ };
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+ };
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+ port@1 {
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+ reg = <1>;
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+ replicator_out_port1: endpoint {
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+ remote-endpoint = <&etb_in_port>;
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+ };
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+ };
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+ };
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+ in-ports {
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+
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+ port {
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+ replicator_in_port0: endpoint {
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+ remote-endpoint = <&funnel_out_port>;
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+ };
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+ };
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+ };
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+ };
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+
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+ amba: axi {
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+ u-boot,dm-pre-reloc;
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ interrupt-parent = <&intc>;
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+ ranges;
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+
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+ adc: adc@f8007100 {
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+ compatible = "xlnx,zynq-xadc-1.00.a";
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+ reg = <0xf8007100 0x20>;
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+ interrupts = <0 7 4>;
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+ interrupt-parent = <&intc>;
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+ clocks = <&clkc 12>;
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+ };
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+
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+ can0: can@e0008000 {
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+ compatible = "xlnx,zynq-can-1.0";
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+ status = "disabled";
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+ clocks = <&clkc 19>, <&clkc 36>;
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+ clock-names = "can_clk", "pclk";
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+ reg = <0xe0008000 0x1000>;
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+ interrupts = <0 28 4>;
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+ interrupt-parent = <&intc>;
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+ tx-fifo-depth = <0x40>;
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+ rx-fifo-depth = <0x40>;
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+ };
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+
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+ can1: can@e0009000 {
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+ compatible = "xlnx,zynq-can-1.0";
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+ status = "disabled";
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+ clocks = <&clkc 20>, <&clkc 37>;
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+ clock-names = "can_clk", "pclk";
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+ reg = <0xe0009000 0x1000>;
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+ interrupts = <0 51 4>;
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+ interrupt-parent = <&intc>;
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+ tx-fifo-depth = <0x40>;
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+ rx-fifo-depth = <0x40>;
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+ };
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+
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+ gpio0: gpio@e000a000 {
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+ compatible = "xlnx,zynq-gpio-1.0";
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+ #gpio-cells = <2>;
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+ clocks = <&clkc 42>;
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+ gpio-controller;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 20 4>;
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+ reg = <0xe000a000 0x1000>;
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+ };
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+
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+ i2c0: i2c@e0004000 {
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+ compatible = "cdns,i2c-r1p10";
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+ status = "disabled";
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+ clocks = <&clkc 38>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 25 4>;
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+ reg = <0xe0004000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ i2c1: i2c@e0005000 {
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+ compatible = "cdns,i2c-r1p10";
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+ status = "disabled";
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+ clocks = <&clkc 39>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 48 4>;
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+ reg = <0xe0005000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ intc: interrupt-controller@f8f01000 {
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+ compatible = "arm,cortex-a9-gic";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ reg = <0xF8F01000 0x1000>,
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+ <0xF8F00100 0x100>;
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+ };
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+
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+ L2: cache-controller@f8f02000 {
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+ compatible = "arm,pl310-cache";
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+ reg = <0xF8F02000 0x1000>;
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+ interrupts = <0 2 4>;
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+ arm,data-latency = <3 2 2>;
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+ arm,tag-latency = <2 2 2>;
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+ cache-unified;
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+ cache-level = <2>;
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+ };
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+
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+ mc: memory-controller@f8006000 {
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+ compatible = "xlnx,zynq-ddrc-a05";
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+ reg = <0xf8006000 0x1000>;
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+ };
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+
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+ ocm: sram@fffc0000 {
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+ compatible = "mmio-sram";
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+ reg = <0xfffc0000 0x10000>;
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+ };
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+
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+ uart0: serial@e0000000 {
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+ compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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+ status = "disabled";
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+ clocks = <&clkc 23>, <&clkc 40>;
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+ clock-names = "uart_clk", "pclk";
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+ reg = <0xE0000000 0x1000>;
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+ interrupts = <0 27 4>;
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+ };
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+
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+ uart1: serial@e0001000 {
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+ compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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+ status = "disabled";
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+ clocks = <&clkc 24>, <&clkc 41>;
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+ clock-names = "uart_clk", "pclk";
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+ reg = <0xE0001000 0x1000>;
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+ interrupts = <0 50 4>;
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+ };
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+
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+ spi0: spi@e0006000 {
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+ compatible = "xlnx,zynq-spi-r1p6";
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+ reg = <0xe0006000 0x1000>;
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+ status = "disabled";
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 26 4>;
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+ clocks = <&clkc 25>, <&clkc 34>;
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+ clock-names = "ref_clk", "pclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@e0007000 {
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+ compatible = "xlnx,zynq-spi-r1p6";
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+ reg = <0xe0007000 0x1000>;
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+ status = "disabled";
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 49 4>;
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+ clocks = <&clkc 26>, <&clkc 35>;
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+ clock-names = "ref_clk", "pclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ qspi: spi@e000d000 {
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+ clock-names = "ref_clk", "pclk";
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+ clocks = <&clkc 10>, <&clkc 43>;
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+ compatible = "xlnx,zynq-qspi-1.0";
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+ status = "disabled";
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 19 4>;
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+ reg = <0xe000d000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ gem0: ethernet@e000b000 {
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+ compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem";
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+ reg = <0xe000b000 0x1000>;
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+ status = "disabled";
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+ interrupts = <0 22 4>;
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+ clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
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+ clock-names = "pclk", "hclk", "tx_clk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ gem1: ethernet@e000c000 {
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+ compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem";
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+ reg = <0xe000c000 0x1000>;
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+ status = "disabled";
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+ interrupts = <0 45 4>;
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+ clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
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+ clock-names = "pclk", "hclk", "tx_clk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ smcc: memory-controller@e000e000 {
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+ compatible = "arm,pl353-smc-r2p1", "arm,primecell";
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+ reg = <0xe000e000 0x0001000>;
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+ status = "disabled";
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+ clock-names = "memclk", "apb_pclk";
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+ clocks = <&clkc 11>, <&clkc 44>;
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+ ranges = <0x0 0x0 0xe1000000 0x1000000
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+ 0x1 0x0 0xe2000000 0x2000000
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+ 0x2 0x0 0xe4000000 0x2000000>;
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 18 4>;
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+ nfc0: nand-controller@0,0 {
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+ compatible = "arm,pl353-nand-r2p1";
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+ reg = <0 0 0x1000000>;
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+ status = "disabled";
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+ #address-cells = <0x1>;
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+ #size-cells = <0x0>;
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+ };
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+ nor0: flash@1,0 {
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+ status = "disabled";
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+ compatible = "cfi-flash";
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+ reg = <1 0 0x2000000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ };
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+ };
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+
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+ sdhci0: mmc@e0100000 {
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+ compatible = "arasan,sdhci-8.9a";
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+ status = "disabled";
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+ clock-names = "clk_xin", "clk_ahb";
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+ clocks = <&clkc 21>, <&clkc 32>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 24 4>;
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+ reg = <0xe0100000 0x1000>;
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+ };
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+
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+ sdhci1: mmc@e0101000 {
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+ compatible = "arasan,sdhci-8.9a";
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+ status = "disabled";
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+ clock-names = "clk_xin", "clk_ahb";
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+ clocks = <&clkc 22>, <&clkc 33>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 47 4>;
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+ reg = <0xe0101000 0x1000>;
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+ };
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+
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+ slcr: slcr@f8000000 {
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+ u-boot,dm-pre-reloc;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
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+ reg = <0xF8000000 0x1000>;
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+ ranges;
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+ clkc: clkc@100 {
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+ u-boot,dm-pre-reloc;
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+ #clock-cells = <1>;
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+ compatible = "xlnx,ps7-clkc";
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+ fclk-enable = <0xf>;
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+ clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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+ "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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+ "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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+ "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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+ "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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+ "dma", "usb0_aper", "usb1_aper", "gem0_aper",
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+ "gem1_aper", "sdio0_aper", "sdio1_aper",
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+ "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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+ "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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+ "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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+ "dbg_trc", "dbg_apb";
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+ reg = <0x100 0x100>;
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+ };
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+
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+ rstc: rstc@200 {
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+ compatible = "xlnx,zynq-reset";
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+ reg = <0x200 0x48>;
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+ #reset-cells = <1>;
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+ syscon = <&slcr>;
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+ };
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+
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+ pinctrl0: pinctrl@700 {
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+ compatible = "xlnx,pinctrl-zynq";
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+ reg = <0x700 0x200>;
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+ syscon = <&slcr>;
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+ };
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+ };
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+
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+ dmac_s: dmac@f8003000 {
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+ compatible = "arm,pl330", "arm,primecell";
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+ reg = <0xf8003000 0x1000>;
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+ interrupt-parent = <&intc>;
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+ interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
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+ "dma4", "dma5", "dma6", "dma7";
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+ interrupts = <0 13 4>,
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+ <0 14 4>, <0 15 4>,
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+ <0 16 4>, <0 17 4>,
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+ <0 40 4>, <0 41 4>,
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+ <0 42 4>, <0 43 4>;
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+ #dma-cells = <1>;
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+ #dma-channels = <8>;
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+ #dma-requests = <4>;
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+ clocks = <&clkc 27>;
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+ clock-names = "apb_pclk";
|
||||
+ };
|
||||
+
|
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+ devcfg: devcfg@f8007000 {
|
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+ compatible = "xlnx,zynq-devcfg-1.0";
|
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+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 8 4>;
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+ reg = <0xf8007000 0x100>;
|
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+ clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
|
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+ clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
|
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+ syscon = <&slcr>;
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+ };
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+
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+ efuse: efuse@f800d000 {
|
||||
+ compatible = "xlnx,zynq-efuse";
|
||||
+ reg = <0xf800d000 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ global_timer: timer@f8f00200 {
|
||||
+ compatible = "arm,cortex-a9-global-timer";
|
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+ reg = <0xf8f00200 0x20>;
|
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+ interrupts = <1 11 0x301>;
|
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+ interrupt-parent = <&intc>;
|
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+ clocks = <&clkc 4>;
|
||||
+ };
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+
|
||||
+ ttc0: timer@f8001000 {
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
|
||||
+ compatible = "cdns,ttc";
|
||||
+ clocks = <&clkc 6>;
|
||||
+ reg = <0xF8001000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ ttc1: timer@f8002000 {
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
|
||||
+ compatible = "cdns,ttc";
|
||||
+ clocks = <&clkc 6>;
|
||||
+ reg = <0xF8002000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ scutimer: timer@f8f00600 {
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1 13 0x301>;
|
||||
+ compatible = "arm,cortex-a9-twd-timer";
|
||||
+ reg = <0xf8f00600 0x20>;
|
||||
+ clocks = <&clkc 4>;
|
||||
+ };
|
||||
+
|
||||
+ usb0: usb@e0002000 {
|
||||
+ compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
|
||||
+ status = "disabled";
|
||||
+ clocks = <&clkc 28>;
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 21 4>;
|
||||
+ reg = <0xe0002000 0x1000>;
|
||||
+ phy_type = "ulpi";
|
||||
+ };
|
||||
+
|
||||
+ usb1: usb@e0003000 {
|
||||
+ compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
|
||||
+ status = "disabled";
|
||||
+ clocks = <&clkc 29>;
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 44 4>;
|
||||
+ reg = <0xe0003000 0x1000>;
|
||||
+ phy_type = "ulpi";
|
||||
+ };
|
||||
+
|
||||
+ watchdog0: watchdog@f8005000 {
|
||||
+ clocks = <&clkc 45>;
|
||||
+ compatible = "cdns,wdt-r1p2";
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <0 9 1>;
|
||||
+ reg = <0xf8005000 0x1000>;
|
||||
+ timeout-sec = <10>;
|
||||
+ };
|
||||
+
|
||||
+ etb@f8801000 {
|
||||
+ compatible = "arm,coresight-etb10", "arm,primecell";
|
||||
+ reg = <0xf8801000 0x1000>;
|
||||
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
+ in-ports {
|
||||
+ port {
|
||||
+ etb_in_port: endpoint {
|
||||
+ remote-endpoint = <&replicator_out_port1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tpiu@f8803000 {
|
||||
+ compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
+ reg = <0xf8803000 0x1000>;
|
||||
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
+ in-ports {
|
||||
+ port {
|
||||
+ tpiu_in_port: endpoint {
|
||||
+ remote-endpoint = <&replicator_out_port0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ funnel@f8804000 {
|
||||
+ compatible = "arm,coresight-static-funnel", "arm,primecell";
|
||||
+ reg = <0xf8804000 0x1000>;
|
||||
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
+
|
||||
+
|
||||
+ out-ports {
|
||||
+ port {
|
||||
+ funnel_out_port: endpoint {
|
||||
+ remote-endpoint =
|
||||
+ <&replicator_in_port0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ in-ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+
|
||||
+ port@0 {
|
||||
+ reg = <0>;
|
||||
+ funnel0_in_port0: endpoint {
|
||||
+ remote-endpoint = <&ptm0_out_port>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ port@1 {
|
||||
+ reg = <1>;
|
||||
+ funnel0_in_port1: endpoint {
|
||||
+ remote-endpoint = <&ptm1_out_port>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ port@2 {
|
||||
+ reg = <2>;
|
||||
+ funnel0_in_port2: endpoint {
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ptm@f889c000 {
|
||||
+ compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
+ reg = <0xf889c000 0x1000>;
|
||||
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
+ cpu = <&cpu0>;
|
||||
+ out-ports {
|
||||
+ port {
|
||||
+ ptm0_out_port: endpoint {
|
||||
+ remote-endpoint = <&funnel0_in_port0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ptm@f889d000 {
|
||||
+ compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
+ reg = <0xf889d000 0x1000>;
|
||||
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
|
||||
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
|
||||
+ cpu = <&cpu1>;
|
||||
+ out-ports {
|
||||
+ port {
|
||||
+ ptm1_out_port: endpoint {
|
||||
+ remote-endpoint = <&funnel0_in_port1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+# 10 "system-top.dts" 2
|
||||
+# 1 "pcw.dtsi" 1
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+/ {
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ operating-points = <500000 1000000 250000 1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+&gem0 {
|
||||
+ enet-reset = <&gpio0 50 0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ status = "okay";
|
||||
+ xlnx,ptp-enet-clock = <0x4f790d8>;
|
||||
+};
|
||||
+&gpio0 {
|
||||
+ emio-gpio-width = <64>;
|
||||
+ gpio-mask-high = <0x0>;
|
||||
+ gpio-mask-low = <0x5600>;
|
||||
+};
|
||||
+&i2c0 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&i2c1 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&intc {
|
||||
+ num_cpus = <2>;
|
||||
+ num_interrupts = <96>;
|
||||
+};
|
||||
+&qspi {
|
||||
+ is-dual = <0>;
|
||||
+ num-cs = <1>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&sdhci0 {
|
||||
+ status = "okay";
|
||||
+ xlnx,has-cd = <0x0>;
|
||||
+ xlnx,has-power = <0x0>;
|
||||
+ xlnx,has-wp = <0x0>;
|
||||
+};
|
||||
+&spi0 {
|
||||
+ is-decoded-cs = <0>;
|
||||
+ num-cs = <3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&spi1 {
|
||||
+ is-decoded-cs = <0>;
|
||||
+ num-cs = <3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&uart0 {
|
||||
+ cts-override ;
|
||||
+ device_type = "serial";
|
||||
+ port-number = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&usb0 {
|
||||
+ phy_type = "ulpi";
|
||||
+ status = "okay";
|
||||
+ usb-reset = <&gpio0 51 0>;
|
||||
+};
|
||||
+&clkc {
|
||||
+ fclk-enable = <0x0>;
|
||||
+ ps-clk-frequency = <33333333>;
|
||||
+};
|
||||
+# 11 "system-top.dts" 2
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ bootargs = "earlycon";
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+ aliases {
|
||||
+ ethernet0 = &gem0;
|
||||
+ i2c0 = &i2c0;
|
||||
+ i2c1 = &i2c1;
|
||||
+ serial0 = &uart0;
|
||||
+ spi0 = &qspi;
|
||||
+ spi1 = &spi0;
|
||||
+ spi2 = &spi1;
|
||||
+ };
|
||||
+ memory {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x40000000>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
|
||||
index 474abc7f6b..764c0237d7 100644
|
||||
index 474abc7f6b..5fc86fabfe 100644
|
||||
--- a/configs/xilinx_zynq_virt_defconfig
|
||||
+++ b/configs/xilinx_zynq_virt_defconfig
|
||||
@@ -6,7 +6,7 @@ CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_ENV_OFFSET=0xE00000
|
||||
CONFIG_DM_GPIO=y
|
||||
-CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="fast-servo"
|
||||
CONFIG_SPL_STACK_R_ADDR=0x200000
|
||||
CONFIG_SPL_STACK=0xfffffe00
|
||||
CONFIG_SPL=y
|
||||
@@ -80,6 +80,7 @@ CONFIG_CMD_MTDPARTS_SPREAD=y
|
||||
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_BOARD=y
|
||||
+CONFIG_SYS_CONFIG_NAME="fast-servo"
|
||||
CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
diff --git a/include/configs/fast-servo.h b/include/configs/fast-servo.h
|
||||
new file mode 100644
|
||||
index 0000000000..0aa486a2b7
|
||||
--- /dev/null
|
||||
+++ b/include/configs/fast-servo.h
|
||||
@@ -0,0 +1 @@
|
||||
+#include <configs/zynq-common.h>
|
||||
|
|
|
|||
11
flake.nix
11
flake.nix
|
|
@ -238,18 +238,19 @@
|
|||
rm -rf $DTSDIR
|
||||
'';
|
||||
|
||||
u-boot = { board ? "zc706" }: pkgs.pkgsCross.armv7l-hf-multiplatform.buildUBoot {
|
||||
u-boot = { board ? "zc706" }: (pkgs.pkgsCross.armv7l-hf-multiplatform.buildUBoot {
|
||||
defconfig = "xilinx_zynq_virt_defconfig";
|
||||
patches = [] ++ pkgs.lib.optional (board == "fast-servo") ./fast-servo/u-boot.patch;
|
||||
preConfigure = ''
|
||||
export DEVICE_TREE=$([ "${board}" = "zc706" ] && echo "zynq-${board}" || echo "${board}")
|
||||
'';
|
||||
extraConfig = ''
|
||||
CONFIG_SYS_PROMPT="${board}-boot> "
|
||||
CONFIG_AUTOBOOT=y
|
||||
CONFIG_BOOTCOMMAND="${builtins.replaceStrings [ "\n" ] [ "; " ] ''
|
||||
setenv bootargs 'root=/dev/mmcblk0p2 console=ttyPS0,115200n8 systemConfig=${builtins.unsafeDiscardStringContext not-os-cfg.build.toplevel}'
|
||||
fatload mmc 0 0x6400000 uImage
|
||||
fatload mmc 0 0x8000000 devicetree.dtb
|
||||
fatload mmc 0 0x8000000 ${board}.dtb
|
||||
fatload mmc 0 0xA400000 uRamdisk.image.gz
|
||||
bootm 0x6400000 0xA400000 0x8000000
|
||||
''}"
|
||||
|
|
@ -258,7 +259,11 @@
|
|||
'';
|
||||
extraMeta.platforms = [ "armv7l-linux" ];
|
||||
filesToInstall = [ "u-boot.elf" ];
|
||||
};
|
||||
}).overrideAttrs (oldAttrs: {
|
||||
postUnpack = ''
|
||||
cp ${dts-support}/fast-servo.dts $sourceRoot/arch/arm/dts/fast-servo.dts
|
||||
'';
|
||||
});
|
||||
|
||||
# Pinned qemu version due to networking errors in recent version 8.2.0
|
||||
qemu = pkgs.qemu.overrideAttrs (oldAttrs: rec {
|
||||
|
|
|
|||
Loading…
Reference in New Issue