291 lines
10 KiB
Python
291 lines
10 KiB
Python
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# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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import os
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from migen import *
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from misoc.interconnect import csr_bus
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from misoc.interconnect.csr import AutoCSR, CSRStorage
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from fast_servo.gateware.cores.adc import ADC, AUX_ADC_CTRL
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from fast_servo.gateware.cores.dac import AUX_DAC_CTRL, DAC
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from fast_servo.gateware.cores.pitaya_ps import Axi2Sys, Sys2CSR, SysCDC, SysInterconnect
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from fast_servo.gateware.cores.ps7 import PS7
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from fast_servo.gateware.cores.spi_phy import SpiInterface, SpiPhy
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class CRG(Module):
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def __init__(self, platform):
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self.ps_rst = Signal()
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self.locked = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_double = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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# Clk.
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 10.0)
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self.clkin = clk100
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clk100_buf = Signal()
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self.specials += Instance("IBUFG", i_I=clk100, o_O=clk100_buf)
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clk_feedback = Signal()
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clk_feedback_buf = Signal()
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clk_sys = Signal()
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clk_idelay = Signal()
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self.specials += [
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Instance(
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"PLLE2_BASE",
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p_BANDWIDTH="OPTIMIZED",
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p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_PHASE=0.0,
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p_CLKFBOUT_MULT=10,
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p_CLKIN1_PERIOD=10.0,
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p_REF_JITTER1=0.01,
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p_STARTUP_WAIT="FALSE",
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i_CLKIN1=clk100_buf,
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i_PWRDWN=0,
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i_RST=self.ps_rst,
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i_CLKFBIN=clk_feedback_buf,
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o_CLKFBOUT=clk_feedback,
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p_CLKOUT0_DIVIDE=10,
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p_CLKOUT0_PHASE=0.0,
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p_CLKOUT0_DUTY_CYCLE=0.5,
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o_CLKOUT0=clk_sys, # 100 MHz <- sys_clk
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p_CLKOUT1_DIVIDE=5,
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p_CLKOUT1_PHASE=0.0,
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p_CLKOUT1_DUTY_CYCLE=0.5,
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o_CLKOUT1=clk_idelay, # 200 MHZ <- 2 * sys_clk = 2*100 MHz
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o_LOCKED=self.locked,
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)
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]
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self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
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self.specials += Instance("BUFG", i_I=clk_sys, o_O=self.cd_sys.clk)
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self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_idelay.clk)
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self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_sys_double.clk)
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# Ignore sys_clk to pll clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, self.clkin)
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self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_sys.clk, o_Q=self.cd_sys.rst)
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class BaseSoC(PS7, AutoCSR):
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def __init__(self, platform, passthrouh=False):
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PS7.__init__(self, platform)
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# TODO:
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# LINIEN SPECIFIC csr_map - in the future should be moved
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# to csr_devices list
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self.csr_map = {
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"adc": 9,
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"fp_led0": 10,
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"fp_led1": 11,
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"fp_led2": 12,
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"fp_led3": 13,
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"dac": 14,
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"adc_aux_ctrl": 15,
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"dac_aux_ctrl": 16,
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}
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self.soc_name = "FastServo"
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self.interconnect_slaves = []
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self.csr_devices = []
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self.platform = platform
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self.submodules.crg = CRG(platform)
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# # # AXI to system bus bridge
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self.submodules.axi2sys = Axi2Sys()
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self.submodules.sys2csr = Sys2CSR()
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self.submodules.syscdc = SysCDC()
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self.add_axi_gp_master(self.axi2sys.axi)
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self.comb += [
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self.axi2sys.axi.aclk.eq(ClockSignal("sys")),
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self.axi2sys.axi.arstn.eq(self.frstn),
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self.syscdc.target.connect(self.sys2csr.sys),
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]
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# ETH LEDS
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self.comb += [
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platform.request("eth_led", 0).eq(platform.request("from_eth_phy", 0)),
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platform.request("eth_led", 1).eq(platform.request("from_eth_phy", 1)),
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]
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# I2C0 to Si5340 on Fast Servo
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self.add_i2c_emio(platform, "ps7_i2c", 0)
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# SPI0 - interface to main ADC and auxiliary ADC
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self.add_spi_interface(platform, SpiInterface.ADC)
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# SPI1 - interface to main DAC and auxiliary DAC
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self.add_spi_interface(platform, SpiInterface.DAC)
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# self.add_main_adc(platform)
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self.submodules.adc = ADC(platform)
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self.csr_devices.append("adc")
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# self.add_main_dac(platform)
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self.submodules.dac = DAC(platform)
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self.csr_devices.append("dac")
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# DEBUG
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if passthrouh:
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DAC_DATA_WIDTH = 14
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for ch in range(2):
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saturate = Signal()
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adc_signal = self.adc.data_out[ch]
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self.comb += [
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saturate.eq(adc_signal[-3:] != Replicate(adc_signal[-1], 3)),
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self.dac.data_in[ch].eq(Mux(saturate,
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Cat(Replicate(~adc_signal[-1], DAC_DATA_WIDTH-1), adc_signal[-1]),
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adc_signal[:-2]))
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]
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si_5340_nrst = platform.request("nrst")
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self.comb += si_5340_nrst.eq(1)
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for i in range(4):
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led_pin = platform.request("fp_led", i)
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setattr(self.submodules, f"fp_led{i}", LED(led_pin))
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self.csr_devices.append(f"fp_led{i}")
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self.submodules.adc_aux_ctrl = AUX_ADC_CTRL(platform)
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self.csr_devices.append("adc_aux_ctrl")
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self.submodules.dac_aux_ctrl = AUX_DAC_CTRL(platform)
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self.csr_devices.append("dac_aux_ctrl")
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def add_spi_interface(self, platform, spi_type):
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assert isinstance(spi_type, SpiInterface)
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n = spi_type.value
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ps7_spi_pads = platform.request("spi", spi_type.value)
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spi_phy = SpiPhy(spi_type, ps7_spi_pads)
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self.submodules += spi_phy
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ps7_config_spi = {
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f"PCW_SPI{n}_GRP_SS0_ENABLE" : "1",
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f"PCW_SPI{n}_GRP_SS0_IO" : "EMIO",
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f"PCW_SPI{n}_GRP_SS1_ENABLE" : "1",
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f"PCW_SPI{n}_GRP_SS1_IO" : "EMIO",
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f"PCW_SPI{n}_GRP_SS2_ENABLE" : "1",
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f"PCW_SPI{n}_GRP_SS2_IO" : "EMIO",
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f"PCW_SPI{n}_PERIPHERAL_ENABLE" : "1",
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f"PCW_SPI{n}_SPI{n}_IO" : "EMIO",
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f"PCW_SPI_PERIPHERAL_CLKSRC" : "IO PLL",
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f"PCW_SPI_PERIPHERAL_DIVISOR0" : "10",
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f"PCW_SPI_PERIPHERAL_FREQMHZ" : "166.666666",
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}
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self.add_ps7_config(ps7_config_spi)
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self.cpu_params.update({
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f"o_SPI{n}_MISO_O" : spi_phy.ps_miso_o,
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f"o_SPI{n}_MISO_T" : spi_phy.ps_miso_t,
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f"o_SPI{n}_MOSI_O" : spi_phy.ps_mosi_o,
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f"o_SPI{n}_MOSI_T" : spi_phy.ps_mosi_t,
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f"o_SPI{n}_SCLK_O" : spi_phy.ps_sclk_o,
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f"o_SPI{n}_SCLK_T" : spi_phy.ps_sclk_t,
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f"i_SPI{n}_SCLK_I" : spi_phy.ps_sclk_i,
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f"i_SPI{n}_MOSI_I" : spi_phy.ps_mosi_i,
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f"i_SPI{n}_MISO_I" : spi_phy.ps_miso_i,
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f"i_SPI{n}_SS_I" : spi_phy.ps_ss_i,
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f"o_SPI{n}_SS_O" : spi_phy.ps_ss[0],
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f"o_SPI{n}_SS1_O" : spi_phy.ps_ss[1],
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f"o_SPI{n}_SS2_O" : spi_phy.ps_ss[2],
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f"o_SPI{n}_SS_T" : spi_phy.ps_ss_t,
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})
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def add_interconnect_slave(self, slave):
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self.interconnect_slaves.append(slave)
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def get_csr_dev_address(self, name, memory):
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# TODO: switch to MiSoC-like address retriving from
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# the list of CSR devices
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if memory is not None:
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name = name + "_" + memory.name_override
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try:
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return self.csr_map[name]
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except KeyError:
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return None
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def soc_finalize(self):
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# Overload this method to customize SystemInterconnect
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# and csrbanks - especially useful in Linien
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self.add_interconnect_slave(self.syscdc.source)
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self.submodules.interconnect = SysInterconnect(
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self.axi2sys.sys,
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*self.interconnect_slaves
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)
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self.submodules.csrbanks = csr_bus.CSRBankArray(self,
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self.get_csr_dev_address)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.sys2csr.csr, self.csrbanks.get_buses()
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)
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def do_finalize(self):
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self.soc_finalize()
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PS7.do_finalize(self)
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def build(self, *args, **kwargs):
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self.platform.build(self, *args, **kwargs)
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class LED(Module, AutoCSR):
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def __init__(self, led):
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self.led_out = CSRStorage(1)
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self.comb += led.eq(self.led_out.storage)
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if __name__ == "__main__":
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import subprocess
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from fast_servo.gateware.fast_servo_platform import Platform
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import argparse
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parser = argparse.ArgumentParser()
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parser.add_argument("--debug", action="store_true", default=False, help="Hardwire ADC data to DAC")
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args = parser.parse_args()
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root_path = os.getcwd()
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platform = Platform()
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fast_servo = BaseSoC(platform, passthrouh=args.debug)
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build_dir = "builds/fast_servo_gw_debug" if args.debug else"builds/fast_servo_gw"
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build_name = "top"
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fast_servo.build(build_dir=build_dir, build_name=build_name, run=True)
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os.chdir(os.path.join(root_path, build_dir))
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with open(f"{build_name}.bif", "w") as f:
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f.write(f"all:\n{{\n\t{build_name}.bit\n}}")
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cmd = f"bootgen -image {build_name}.bif -arch zynq -process_bitstream bin -w on".split(" ")
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subprocess.run(cmd)
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