386 lines
12 KiB
Python
386 lines
12 KiB
Python
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# Copyright 2014-2015 Robert Jördens <jordens@gmail.com>
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# Copyright 2018-2022 Benjamin Wiegand <benjamin.wiegand@physik.hu-berlin.de>
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# Copyright 2021-2022 Bastian Leykauf <leykauf@physik.hu-berlin.de>
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# Copyright 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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#
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# This file is part of Fast Servo Software Package and is based on Linien.
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#
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# Linien is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# Linien is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with Linien. If not, see <http://www.gnu.org/licenses/>.
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from functools import reduce
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from operator import or_
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from migen import (
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DIR_M_TO_S,
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DIR_S_TO_M,
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Cat,
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ClockSignal,
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If,
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Instance,
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Module,
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Record,
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Replicate,
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ResetSignal,
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Signal,
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)
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from misoc.interconnect import csr_bus, wishbone
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sys_layout = [
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("rstn", 1, DIR_M_TO_S),
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("clk", 1, DIR_M_TO_S),
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("addr", 32, DIR_M_TO_S),
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("wdata", 32, DIR_M_TO_S),
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("sel", 4, DIR_M_TO_S),
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("wen", 1, DIR_M_TO_S),
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("ren", 1, DIR_M_TO_S),
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("rdata", 32, DIR_S_TO_M),
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("err", 1, DIR_S_TO_M),
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("ack", 1, DIR_S_TO_M),
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]
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axi_layout = [
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("arvalid", 1),
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("awvalid", 1),
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("bready", 1),
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("rready", 1),
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("wlast", 1),
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("wvalid", 1),
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("arid", 12),
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("awid", 12),
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("wid", 12),
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("arburst", 2),
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("arlock", 2),
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("arsize", 3),
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("awburst", 2),
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("awlock", 2),
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("awsize", 3),
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("arprot", 3),
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("awprot", 3),
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("araddr", 32),
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("awaddr", 32),
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("wdata", 32),
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("arcache", 4),
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("arlen", 4),
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("arqos", 4),
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("awcache", 4),
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("awlen", 4),
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("awqos", 4),
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("wstrb", 4),
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("aclk", 1),
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("arready", 1),
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("awready", 1),
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("bvalid", 1),
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("rlast", 1),
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("rvalid", 1),
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("wready", 1),
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("bid", 12),
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("rid", 12),
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("bresp", 2),
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("rresp", 2),
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("rdata", 32),
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("arstn", 1),
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]
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class PitayaPS(Module):
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def __init__(self, cpu):
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self.fclk = Signal(4)
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self.frstn = Signal(4)
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###
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self.submodules.axi = Axi2Sys()
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axi = self.axi.axi
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self.comb += [
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axi.aclk.eq(self.fclk[0]),
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axi.arstn.eq(self.frstn[0]),
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]
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self.specials += Instance(
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"system_processing_system7_0_0",
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io_MIO=cpu.mio,
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io_PS_CLK=cpu.ps_clk,
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io_PS_PORB=cpu.ps_porb,
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io_PS_SRSTB=cpu.ps_srstb,
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io_DDR_Addr=cpu.DDR_addr,
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io_DDR_BankAddr=cpu.DDR_ba,
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io_DDR_CAS_n=cpu.DDR_cas_n,
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io_DDR_Clk_n=cpu.DDR_ck_n,
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io_DDR_Clk=cpu.DDR_ck_p,
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io_DDR_CKE=cpu.DDR_cke,
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io_DDR_CS_n=cpu.DDR_cs_n,
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io_DDR_DM=cpu.DDR_dm,
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io_DDR_DQ=cpu.DDR_dq,
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io_DDR_DQS_n=cpu.DDR_dqs_n,
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io_DDR_DQS=cpu.DDR_dqs_p,
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io_DDR_ODT=cpu.DDR_odt,
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io_DDR_RAS_n=cpu.DDR_ras_n,
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io_DDR_DRSTB=cpu.DDR_reset_n,
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io_DDR_WEB=cpu.DDR_we_n,
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io_DDR_VRN=cpu.ddr_vrn,
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io_DDR_VRP=cpu.ddr_vrp,
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o_FCLK_CLK0=self.fclk[0],
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o_FCLK_CLK1=self.fclk[1],
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o_FCLK_CLK2=self.fclk[2],
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o_FCLK_CLK3=self.fclk[3],
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o_FCLK_RESET0_N=self.frstn[0],
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o_FCLK_RESET1_N=self.frstn[1],
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o_FCLK_RESET2_N=self.frstn[2],
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o_FCLK_RESET3_N=self.frstn[3],
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i_M_AXI_GP0_ACLK=axi.aclk,
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o_M_AXI_GP0_ARVALID=axi.arvalid,
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o_M_AXI_GP0_AWVALID=axi.awvalid,
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o_M_AXI_GP0_BREADY=axi.bready,
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o_M_AXI_GP0_RREADY=axi.rready,
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o_M_AXI_GP0_WLAST=axi.wlast,
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o_M_AXI_GP0_WVALID=axi.wvalid,
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o_M_AXI_GP0_ARID=axi.arid,
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o_M_AXI_GP0_AWID=axi.awid,
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o_M_AXI_GP0_WID=axi.wid,
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o_M_AXI_GP0_ARBURST=axi.arburst,
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o_M_AXI_GP0_ARLOCK=axi.arlock,
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o_M_AXI_GP0_ARSIZE=axi.arsize,
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o_M_AXI_GP0_AWBURST=axi.awburst,
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o_M_AXI_GP0_AWLOCK=axi.awlock,
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o_M_AXI_GP0_AWSIZE=axi.awsize,
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o_M_AXI_GP0_ARPROT=axi.arprot,
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o_M_AXI_GP0_AWPROT=axi.awprot,
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o_M_AXI_GP0_ARADDR=axi.araddr,
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o_M_AXI_GP0_AWADDR=axi.awaddr,
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o_M_AXI_GP0_WDATA=axi.wdata,
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o_M_AXI_GP0_ARCACHE=axi.arcache,
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o_M_AXI_GP0_ARLEN=axi.arlen,
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o_M_AXI_GP0_ARQOS=axi.arqos,
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o_M_AXI_GP0_AWCACHE=axi.awcache,
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o_M_AXI_GP0_AWLEN=axi.awlen,
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o_M_AXI_GP0_AWQOS=axi.awqos,
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o_M_AXI_GP0_WSTRB=axi.wstrb,
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i_M_AXI_GP0_ARREADY=axi.arready,
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i_M_AXI_GP0_AWREADY=axi.awready,
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i_M_AXI_GP0_BVALID=axi.bvalid,
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i_M_AXI_GP0_RLAST=axi.rlast,
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i_M_AXI_GP0_RVALID=axi.rvalid,
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i_M_AXI_GP0_WREADY=axi.wready,
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i_M_AXI_GP0_BID=axi.bid,
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i_M_AXI_GP0_RID=axi.rid,
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i_M_AXI_GP0_BRESP=axi.bresp,
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i_M_AXI_GP0_RRESP=axi.rresp,
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i_M_AXI_GP0_RDATA=axi.rdata,
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i_SPI0_SS_I=0,
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# i_SPI0_SS_I=spi.ss_i,
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# o_SPI0_SS_O=spi.ss_o,
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# o_SPI0_SS_T=spi.ss_t,
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# o_SPI0_SS1_O=spi.ss1_o,
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# o_SPI0_SS2_O=spi.ss2_o,
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i_SPI0_SCLK_I=0,
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# i_SPI0_SCLK_I=spi.sclk_i,
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# o_SPI0_SCLK_O=spi.sclk_o,
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# o_SPI0_SCLK_T=spi.sclk_t,
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i_SPI0_MOSI_I=0,
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# i_SPI0_MOSI_I=spi.mosi_i,
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# o_SPI0_MOSI_O=spi.mosi_o,
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# o_SPI0_MOSI_T=spi.mosi_t,
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i_SPI0_MISO_I=0,
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# i_SPI0_MISO_I=spi.miso_i,
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# o_SPI0_MISO_O=spi.miso_o,
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# o_SPI0_MISO_T=spi.miso_t,
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i_USB0_VBUS_PWRFAULT=0,
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)
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class Axi2Sys(Module):
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def __init__(self):
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self.sys = Record(sys_layout)
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self.axi = Record(axi_layout)
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###
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self.comb += [self.sys.clk.eq(self.axi.aclk), self.sys.rstn.eq(self.axi.arstn)]
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self.specials += Instance(
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"axi_slave",
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p_AXI_DW=32,
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p_AXI_AW=32,
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p_AXI_IW=12,
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i_axi_clk_i=self.axi.aclk,
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i_axi_rstn_i=self.axi.arstn,
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i_axi_awid_i=self.axi.awid,
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i_axi_awaddr_i=self.axi.awaddr,
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i_axi_awlen_i=self.axi.awlen,
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i_axi_awsize_i=self.axi.awsize,
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i_axi_awburst_i=self.axi.awburst,
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i_axi_awlock_i=self.axi.awlock,
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i_axi_awcache_i=self.axi.awcache,
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i_axi_awprot_i=self.axi.awprot,
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i_axi_awvalid_i=self.axi.awvalid,
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o_axi_awready_o=self.axi.awready,
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i_axi_wid_i=self.axi.wid,
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i_axi_wdata_i=self.axi.wdata,
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i_axi_wstrb_i=self.axi.wstrb,
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i_axi_wlast_i=self.axi.wlast,
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i_axi_wvalid_i=self.axi.wvalid,
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o_axi_wready_o=self.axi.wready,
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o_axi_bid_o=self.axi.bid,
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o_axi_bresp_o=self.axi.bresp,
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o_axi_bvalid_o=self.axi.bvalid,
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i_axi_bready_i=self.axi.bready,
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i_axi_arid_i=self.axi.arid,
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i_axi_araddr_i=self.axi.araddr,
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i_axi_arlen_i=self.axi.arlen,
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i_axi_arsize_i=self.axi.arsize,
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i_axi_arburst_i=self.axi.arburst,
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i_axi_arlock_i=self.axi.arlock,
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i_axi_arcache_i=self.axi.arcache,
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i_axi_arprot_i=self.axi.arprot,
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i_axi_arvalid_i=self.axi.arvalid,
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o_axi_arready_o=self.axi.arready,
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o_axi_rid_o=self.axi.rid,
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o_axi_rdata_o=self.axi.rdata,
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o_axi_rresp_o=self.axi.rresp,
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o_axi_rlast_o=self.axi.rlast,
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o_axi_rvalid_o=self.axi.rvalid,
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i_axi_rready_i=self.axi.rready,
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o_sys_addr_o=self.sys.addr,
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o_sys_wdata_o=self.sys.wdata,
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o_sys_sel_o=self.sys.sel,
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o_sys_wen_o=self.sys.wen,
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o_sys_ren_o=self.sys.ren,
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i_sys_rdata_i=self.sys.rdata,
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i_sys_err_i=self.sys.err,
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i_sys_ack_i=self.sys.ack,
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)
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class SysInterconnect(Module):
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def __init__(self, master, *slaves):
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cs = Signal(max=len(slaves)) if len(slaves) != 1 else Signal()
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self.comb += cs.eq(master.addr[20:23])
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rets = []
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for i, s in enumerate(slaves):
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sel = Signal()
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self.comb += [
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sel.eq(cs == i),
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s.clk.eq(master.clk),
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s.rstn.eq(master.rstn),
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s.addr.eq(master.addr),
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s.wdata.eq(master.wdata),
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s.sel.eq(master.sel),
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s.wen.eq(sel & master.wen),
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s.ren.eq(sel & master.ren),
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]
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ret = Cat(s.err, s.ack, s.rdata)
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rets.append(Replicate(sel, len(ret)) & ret)
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self.comb += Cat(master.err, master.ack, master.rdata).eq(reduce(or_, rets))
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class Sys2Wishbone(Module):
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def __init__(self):
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self.wishbone = wb = wishbone.Interface()
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self.sys = sys = Record(sys_layout)
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###
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sys2 = Record(sys_layout)
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self.specials += Instance(
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"bus_clk_bridge",
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i_sys_clk_i=sys.clk,
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i_sys_rstn_i=sys.rstn,
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i_sys_addr_i=sys.addr,
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i_sys_wdata_i=sys.wdata,
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i_sys_sel_i=sys.sel,
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i_sys_wen_i=sys.wen,
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i_sys_ren_i=sys.ren,
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o_sys_rdata_o=sys.rdata,
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o_sys_err_o=sys.err,
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o_sys_ack_o=sys.ack,
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i_clk_i=ClockSignal(),
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i_rstn_i=~ResetSignal(),
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o_addr_o=sys2.addr,
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o_wen_o=sys2.wen,
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o_ren_o=sys2.ren,
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o_wdata_o=sys2.wdata,
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i_rdata_i=sys2.rdata,
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|
i_err_i=sys2.err,
|
||
|
|
i_ack_i=sys2.ack,
|
||
|
|
)
|
||
|
|
self.sync += [
|
||
|
|
If(
|
||
|
|
sys2.ren | sys2.wen,
|
||
|
|
wb.cyc.eq(1),
|
||
|
|
wb.adr.eq(sys2.addr[2:]),
|
||
|
|
wb.we.eq(sys2.wen),
|
||
|
|
wb.dat_w.eq(sys2.wdata),
|
||
|
|
).Elif(wb.ack, wb.cyc.eq(0))
|
||
|
|
]
|
||
|
|
self.comb += [
|
||
|
|
wb.stb.eq(wb.cyc),
|
||
|
|
sys2.rdata.eq(wb.dat_r),
|
||
|
|
sys2.ack.eq(wb.ack),
|
||
|
|
sys2.err.eq(wb.err),
|
||
|
|
]
|
||
|
|
|
||
|
|
|
||
|
|
class SysCDC(Module):
|
||
|
|
def __init__(self, cd_target="sys"):
|
||
|
|
self.source = Record(sys_layout)
|
||
|
|
self.target = Record(sys_layout)
|
||
|
|
|
||
|
|
self.specials += Instance(
|
||
|
|
"bus_clk_bridge",
|
||
|
|
i_sys_clk_i=self.source.clk,
|
||
|
|
i_sys_rstn_i=self.source.rstn,
|
||
|
|
i_sys_addr_i=self.source.addr,
|
||
|
|
i_sys_wdata_i=self.source.wdata,
|
||
|
|
i_sys_sel_i=self.source.sel,
|
||
|
|
i_sys_wen_i=self.source.wen,
|
||
|
|
i_sys_ren_i=self.source.ren,
|
||
|
|
o_sys_rdata_o=self.source.rdata,
|
||
|
|
o_sys_err_o=self.source.err,
|
||
|
|
o_sys_ack_o=self.source.ack,
|
||
|
|
i_clk_i=self.target.clk,
|
||
|
|
i_rstn_i=self.target.rstn,
|
||
|
|
o_addr_o=self.target.addr,
|
||
|
|
o_wdata_o=self.target.wdata,
|
||
|
|
o_wen_o=self.target.wen,
|
||
|
|
o_ren_o=self.target.ren,
|
||
|
|
i_rdata_i=self.target.rdata,
|
||
|
|
i_err_i=self.target.err,
|
||
|
|
i_ack_i=self.target.ack,
|
||
|
|
)
|
||
|
|
self.comb += [
|
||
|
|
self.target.clk.eq(ClockSignal(cd_target)),
|
||
|
|
self.target.rstn.eq(~ResetSignal(cd_target)),
|
||
|
|
]
|
||
|
|
|
||
|
|
|
||
|
|
class Sys2CSR(Module):
|
||
|
|
def __init__(self):
|
||
|
|
self.csr = csr_bus.Interface()
|
||
|
|
self.sys = Record(sys_layout)
|
||
|
|
|
||
|
|
###
|
||
|
|
|
||
|
|
stb = Signal()
|
||
|
|
self.sync += [
|
||
|
|
stb.eq(self.sys.wen | self.sys.ren),
|
||
|
|
self.csr.adr.eq(self.sys.addr[2:]),
|
||
|
|
self.csr.we.eq(self.sys.wen),
|
||
|
|
self.csr.dat_w.eq(self.sys.wdata),
|
||
|
|
self.sys.ack.eq(stb),
|
||
|
|
self.sys.rdata.eq(self.csr.dat_r),
|
||
|
|
]
|