67 lines
3.3 KiB
Diff
67 lines
3.3 KiB
Diff
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diff --git a/gateware/logic/autolock.py b/gateware/logic/autolock.py
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index a6dc764..1a8407f 100644
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--- a/gateware/logic/autolock.py
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+++ b/gateware/logic/autolock.py
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@@ -148,14 +148,17 @@ class RobustAutolock(Module, AutoCSR):
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final_waited_for = Signal(bits_for(N_points))
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# this is the signal that's used for detecting peaks
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- sum_diff = Signal((len(self.sum_diff_calculator.output), True))
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- abs_sum_diff = Signal.like(sum_diff)
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+ self.sum_diff = Signal((len(self.sum_diff_calculator.output), True))
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+ abs_sum_diff = Signal.like(self.sum_diff)
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self.comb += [
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self.sum_diff_calculator.writing_data_now.eq(self.writing_data_now),
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self.sum_diff_calculator.restart.eq(self.at_start),
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self.sum_diff_calculator.input.eq(self.input),
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self.sum_diff_calculator.delay_value.eq(self.time_scale.storage),
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- sum_diff.eq(self.sum_diff_calculator.output),
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+ ]
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+
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+ self.sync += [
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+ self.sum_diff.eq(self.sum_diff_calculator.output),
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]
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# has this signal at the moment the same sign as the peak we are looking for?
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@@ -168,16 +171,17 @@ class RobustAutolock(Module, AutoCSR):
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all_instructions_triggered = Signal()
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self.comb += [
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- sign_equal.eq((sum_diff > 0) == (current_peak_height > 0)),
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- If(sum_diff >= 0, abs_sum_diff.eq(sum_diff)).Else(
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- abs_sum_diff.eq(-1 * sum_diff)
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+ sign_equal.eq((self.sum_diff > 0) == (current_peak_height > 0)),
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+ If(self.sum_diff >= 0, abs_sum_diff.eq(self.sum_diff)).Else(
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+ abs_sum_diff.eq(-1 * self.sum_diff)
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),
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If(
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current_peak_height >= 0,
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abs_current_peak_height.eq(current_peak_height),
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).Else(abs_current_peak_height.eq(-1 * current_peak_height)),
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over_threshold.eq(abs_sum_diff >= abs_current_peak_height),
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- waited_long_enough.eq(waited_for > current_wait_for),
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+ # HACK: To compensate the lock position output for the pipeline delay
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+ waited_long_enough.eq((waited_for >= current_wait_for - 1) & (waited_for != 2 ** bits_for(N_points) - 1) & (current_wait_for - 1 != 2 ** bits_for(N_points) - 1)),
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all_instructions_triggered.eq(
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self.current_instruction_idx >= self.N_instructions.storage
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),
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@@ -190,7 +194,7 @@ class RobustAutolock(Module, AutoCSR):
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self.sync += [
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If(
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self.at_start,
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- waited_for.eq(0),
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+ waited_for.eq(-1),
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# fpga robust autolock algorithm registeres trigger events delayed.
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# Therefore, we give it a head start for `final_waited_for`
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final_waited_for.eq(ROBUST_AUTOLOCK_FPGA_DELAY),
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@@ -213,7 +217,8 @@ class RobustAutolock(Module, AutoCSR):
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self.current_instruction_idx.eq(
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self.current_instruction_idx + 1
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),
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- waited_for.eq(0),
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+ # HACK: To compensate the lock position output for the pipeline delay
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+ waited_for.eq(-1),
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).Else(waited_for.eq(waited_for + 1)),
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),
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If(
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