nix-servo/fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch

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diff --git a/gateware/linien_module.py b/gateware/linien_module.py
index a64714c..1d905de 100644
--- a/gateware/linien_module.py
+++ b/gateware/linien_module.py
@@ -47,7 +47,7 @@ from .lowlevel.scopegen import ScopeGen
class LinienLogic(Module, AutoCSR):
- def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=25):
+ def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=18):
self.init_csr(width, chain_factor_width)
self.init_submodules(width, signal_width)
self.connect_pid()
@@ -154,7 +154,7 @@ class LinienModule(Module, AutoCSR):
def __init__(self, soc):
width = 14
signal_width = 25
- coeff_width = 25
+ coeff_width = 18
chain_factor_bits = 8
self.init_submodules(