65 lines
2.6 KiB
Diff
65 lines
2.6 KiB
Diff
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diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
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index 4320f94..64e1a74 100644
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--- a/gateware/logic/pid.py
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+++ b/gateware/logic/pid.py
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@@ -56,10 +56,13 @@ class PID(Module, AutoCSR):
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self.comb += [kp_signed.eq(self.kp.storage)]
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kp_mult = Signal((self.width + self.coeff_width, True))
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- self.comb += [kp_mult.eq(self.error * kp_signed)]
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+ kp_mult_reg = Signal((self.width + self.coeff_width, True))
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+ self.sync += kp_mult.eq(kp_mult_reg >> (self.coeff_width - 2))
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+
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+ self.comb += [kp_mult_reg.eq(self.error * kp_signed)]
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self.output_p = Signal((self.width, True))
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- self.comb += [self.output_p.eq(kp_mult >> (self.coeff_width - 2))]
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+ self.comb += [self.output_p.eq(kp_mult)]
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self.kp_mult = kp_mult
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@@ -71,8 +74,10 @@ class PID(Module, AutoCSR):
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self.comb += [ki_signed.eq(self.ki.storage)]
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self.ki_mult = Signal((1 + self.width + self.coeff_width, True))
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+ self.ki_mult_reg = Signal((1 + self.width + self.coeff_width, True))
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+ self.sync += self.ki_mult.eq(self.ki_mult_reg)
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+ self.comb += self.ki_mult_reg.eq((self.error * ki_signed) >> 4)
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- self.comb += [self.ki_mult.eq((self.error * ki_signed) >> 4)]
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int_reg_width = self.width + self.coeff_width + 4
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extra_width = int_reg_width - self.width
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@@ -110,15 +115,17 @@ class PID(Module, AutoCSR):
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self.kd = CSRStorage(self.coeff_width)
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kd_signed = Signal((self.coeff_width, True))
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kd_mult = Signal((mult_width, True))
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+ kd_mult_reg = Signal((mult_width, True))
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+ self.sync += kd_mult.eq(kd_mult_reg)
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- self.comb += [kd_signed.eq(self.kd.storage), kd_mult.eq(self.error * kd_signed)]
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+ self.comb += [kd_signed.eq(self.kd.storage), kd_mult_reg.eq(self.error * kd_signed >> (self.coeff_width - self.d_shift))]
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kd_reg = Signal((out_width, True))
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kd_reg_r = Signal((out_width, True))
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self.output_d = Signal((out_width, True))
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self.sync += [
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- kd_reg.eq(kd_mult >> (self.coeff_width - self.d_shift)),
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+ kd_reg.eq(kd_mult),
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kd_reg_r.eq(kd_reg),
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self.output_d.eq(kd_reg - kd_reg_r),
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]
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@@ -143,4 +150,12 @@ class PID(Module, AutoCSR):
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# sync is required here, otherwise we get artifacts when one of the
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# signals changes sign
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- self.sync += [self.pid_sum.eq(self.output_p + self.int_out + self.output_d)]
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+ self.sync += [
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+ If(
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+ self.running,
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+ self.pid_sum.eq(self.output_p + self.int_out + self.output_d),
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+ )
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+ .Else(self.pid_sum.eq(0))
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+ ]
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