129 lines
3.5 KiB
Coq
129 lines
3.5 KiB
Coq
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/**
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* $Id: bus_clk_bridge.v 961 2014-01-21 11:40:39Z matej.oblak $
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*
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* @brief Red Pitaya system bus clock crossing bridge.
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*
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* @Author Matej Oblak
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*
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* (c) Red Pitaya http://www.redpitaya.com
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*
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* This part of code is written in Verilog hardware description language (HDL).
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* Please visit http://en.wikipedia.org/wiki/Verilog
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* for more details on the language used herein.
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*/
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/**
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* GENERAL DESCRIPTION:
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*
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* Clock domain bridge for system bus.
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*
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*
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* /------\
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* SYSTEM | | PROCESSING
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* BUS <-----> | SYNC | <-----> BUS
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* | |
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* \------/
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*
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*
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* System bus runs on one clock domain while processing runs on separate. To
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* simplify transition of writing and reading data this bridge was created.
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*
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*/
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module bus_clk_bridge
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(
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// system bus
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input sys_clk_i , //!< bus clock
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input sys_rstn_i , //!< bus reset - active low
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input [ 32-1: 0] sys_addr_i , //!< bus address
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input [ 32-1: 0] sys_wdata_i , //!< bus write data
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input [ 4-1: 0] sys_sel_i , //!< bus write byte select
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input sys_wen_i , //!< bus write enable
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input sys_ren_i , //!< bus read enable
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output [ 32-1: 0] sys_rdata_o , //!< bus read data
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output sys_err_o , //!< bus error indicator
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output sys_ack_o , //!< bus acknowledge signal
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// Destination bus
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input clk_i , //!< clock
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input rstn_i , //!< reset - active low
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output reg [ 32-1: 0] addr_o , //!< address
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output reg [ 32-1: 0] wdata_o , //!< write data
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output wen_o , //!< write enable
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output ren_o , //!< read enable
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input [ 32-1: 0] rdata_i , //!< read data
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input err_i , //!< error indicator
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input ack_i //!< acknowledge signal
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);
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//---------------------------------------------------------------------------------
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// Synchronize signals between clock domains
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reg sys_rd ;
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reg sys_wr ;
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reg sys_do ;
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reg [ 2-1: 0] sys_sync ;
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reg sys_done ;
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reg dst_do ;
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reg [ 2-1: 0] dst_sync ;
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reg dst_done ;
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always @(posedge sys_clk_i) begin
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if (sys_rstn_i == 1'b0) begin
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sys_rd <= 1'b0 ;
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sys_wr <= 1'b0 ;
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sys_do <= 1'b0 ;
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sys_sync <= 2'h0 ;
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sys_done <= 1'b0 ;
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end
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else begin
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if ((sys_do == sys_done) && (sys_wen_i || sys_ren_i)) begin
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addr_o <= sys_addr_i ;
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wdata_o <= sys_wdata_i ;
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sys_rd <= sys_ren_i ;
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sys_wr <= sys_wen_i ;
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sys_do <= !sys_do ;
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end
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sys_sync <= {sys_sync[0], dst_done};
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sys_done <= sys_sync[1];
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end
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end
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always @(posedge clk_i) begin
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if (rstn_i == 1'b0) begin
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dst_do <= 1'b0 ;
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dst_sync <= 2'h0 ;
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dst_done <= 1'b0 ;
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end
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else begin
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dst_sync <= {dst_sync[0], sys_do};
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dst_do <= dst_sync[1];
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if (ack_i && (dst_do != dst_done))
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dst_done <= dst_do;
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end
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end
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assign ren_o = sys_rd && (dst_sync[1]^dst_do);
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assign wen_o = sys_wr && (dst_sync[1]^dst_do);
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assign sys_rdata_o = rdata_i ;
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assign sys_err_o = err_i ;
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assign sys_ack_o = sys_done ^ sys_sync[1] ;
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endmodule
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