337 lines
11 KiB
Python
337 lines
11 KiB
Python
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# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2022-2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from migen.build.generic_platform import *
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from migen.build.xilinx import XilinxPlatform
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import os
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from fast_servo.gateware import verilog_dir
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Front panel LEDs
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("fp_led", 0, Pins("G7"), IOStandard("LVCMOS25")),
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("fp_led", 1, Pins("G8"), IOStandard("LVCMOS25")),
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("fp_led", 2, Pins("G2"), IOStandard("LVCMOS25")),
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("fp_led", 3, Pins("G3"), IOStandard("LVCMOS25")),
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# LEDs
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("user_led", 0, Pins("AB16"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AA14"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("AA15"), IOStandard("LVCMOS33")),
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# ETH LEDs
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("eth_led", 0, Pins("V11"), IOStandard("LVCMOS33")),
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("eth_led", 1, Pins("U13"), IOStandard("LVCMOS33")),
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("from_eth_phy", 0, Pins("J3"), IOStandard("LVCMOS18")),
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("from_eth_phy", 1, Pins("K8"), IOStandard("LVCMOS18")),
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# CLK 100 MHz from oscillator
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("clk100", 0, Pins("Y14"), IOStandard("LVCMOS33")),
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# MGT clk from on-board Si5338A
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("mgt_clk1", 0,
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Subsignal("p", Pins("U5")),
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Subsignal("n", Pins("V5")),
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IOStandard("LVDS_25"),
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),
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# FCLK125 from on-board Si5338A
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("fclk125", 0, Pins("K2"), IOStandard("LVCMOS18")),
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# # ADC CLK
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# ("fpga_clk", 0,
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# Subsignal("p", Pins("C6")),
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# Subsignal("n", Pins("C5")),
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# IOStandard("LVDS_25"),
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# ),
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# DAC CLK
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("fpga_clk", 1,
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Subsignal("p", Pins("J7")),
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Subsignal("n", Pins("J6")),
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IOStandard("LVDS_25"),
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),
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# MAIN ADC LT2195
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("adc", 0,
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Subsignal("data0_p", Pins("F7 B7 E4 D1"), IOStandard("LVDS_25")),
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Subsignal("data0_n", Pins("E7 B6 E3 C1"), IOStandard("LVDS_25")),
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Subsignal("data1_p", Pins("A2 D5 F2 D7"), IOStandard("LVDS_25")),
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Subsignal("data1_n", Pins("A1 C4 F1 D6"), IOStandard("LVDS_25")),
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Subsignal("dco_p", Pins("B4"), IOStandard("LVDS_25")),
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Subsignal("dco_n", Pins("B3"), IOStandard("LVDS_25")),
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Subsignal("frame_p", Pins("B2"), IOStandard("LVDS_25")),
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Subsignal("frame_n", Pins("B1"), IOStandard("LVDS_25"))
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),
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# ADC AFE
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("adc_afe", 0,
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Subsignal("ch1_gain", Pins("AA12"), IOStandard("LVCMOS33")),
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Subsignal("ch2_gain", Pins("AB11"), IOStandard("LVCMOS33")),
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Subsignal("nshdn_ch1", Pins("G4"), IOStandard("LVCMOS25")),
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Subsignal("nshdn_ch2", Pins("F4"), IOStandard("LVCMOS25")),
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),
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# P5 R5 N1 N4 L2 P6 N3 R4 P1 L1 M3 M4 U2 T2
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# MAIN DAC AD9117
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("dac", 0,
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Subsignal("data",
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Pins("T2 U2 M4 M3 L1 P1 R4 N3 P6 L2 N4 N1 R5 P5"),
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IOStandard("LVCMOS18")),
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Subsignal("dclkio", Pins("U1"), IOStandard("LVCMOS18")),
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Subsignal("rst", Pins("T1"), IOStandard("LVCMOS18")),
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),
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# DAC AFE
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("dac_afe", 0,
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Subsignal("ch1_pd_n", Pins("L5")),
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Subsignal("ch2_pd_n", Pins("L4")),
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IOStandard("LVCMOS18"),
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),
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# AUXILIARY ADC
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("aux_adc", 0,
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Subsignal("diff_n", Pins("W18")),
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Subsignal("a", Pins("AB18 AB19 W17")),
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Subsignal("range", Pins("U19")),
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IOStandard("LVCMOS33")
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),
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# AUXILIARY DAC
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("aux_dac", 0,
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Subsignal("nclr", Pins("V19")),
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Subsignal("bin", Pins("AA19")),
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Subsignal("nldac", Pins("AB21")),
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IOStandard("LVCMOS33")
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),
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# ADC SPI
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("spi", 0,
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Subsignal("sclk", Pins("J1"), IOStandard("LVCMOS18")),
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Subsignal("mosi", Pins("J5"), IOStandard("LVCMOS18")),
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Subsignal("miso", Pins("K5"), IOStandard("LVCMOS18")),
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Subsignal("cs", Pins("J2"), IOStandard("LVCMOS18")),
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Subsignal("aux_adc_sclk", Pins("AB22"), IOStandard("LVCMOS33")),
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Subsignal("aux_adc_miso_a", Pins("Y18"), IOStandard("LVCMOS33")),
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Subsignal("aux_adc_miso_b", Pins("AA16"), IOStandard("LVCMOS33")),
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Subsignal("aux_adc_cs", Pins("Y19"), IOStandard("LVCMOS33")),
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Subsignal("aux_dac_sclk", Pins("V18"), IOStandard("LVCMOS33")),
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Subsignal("aux_dac_mosi", Pins("U17"), IOStandard("LVCMOS33")),
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Subsignal("aux_dac_miso", Pins("U18"), IOStandard("LVCMOS33")),
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Subsignal("aux_dac_cs", Pins("AA20"), IOStandard("LVCMOS33")),
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),
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# DAC SPI
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("spi", 1,
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Subsignal("sclk", Pins("K3"), IOStandard("LVCMOS18")),
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Subsignal("sdio", Pins("R2"), IOStandard("LVCMOS18")),
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Subsignal("cs", Pins("R3"), IOStandard("LVCMOS18")),
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# Subsignal("sclk_aux", Pins("V18"), IOStandard("LVCMOS33")),
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# Subsignal("mosi_aux", Pins("U17"), IOStandard("LVCMOS33")),
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# Subsignal("miso_aux", Pins("U18"), IOStandard("LVCMOS33")),
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# Subsignal("cs_aux", Pins("AA20"), IOStandard("LVCMOS33")),
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),
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#Pins("Y15 AB14 AB13 V13 V14 V15 U12 W13 W12 R17 W15 AB17 Y12 Y13 V16 W16 AA17 Y17"),
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("gpio", 0,
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Subsignal("n", Pins("Y15 AB14 AB13 V13 V14 V15 U12 W13"), IOStandard("LVCMOS33")),
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Subsignal("p", Pins("W12 R17 W15 AB17 Y12 Y13 V16 W16"), IOStandard("LVCMOS33")),
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),
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# PS7
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("ps7_clk", 0, Pins("_" * 1)),
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("ps7_porb", 0, Pins("_" * 1)),
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("ps7_srstb", 0, Pins("_" * 1)),
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("ps7_mio", 0, Pins("_" * 54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins("_" * 15)),
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Subsignal("ba", Pins("_" * 3)),
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Subsignal("cas_n", Pins("_" * 1)),
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Subsignal("ck_n", Pins("_" * 1)),
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Subsignal("ck_p", Pins("_" * 1)),
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Subsignal("cke", Pins("_" * 1)),
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Subsignal("cs_n", Pins("_" * 1)),
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Subsignal("dm", Pins("_" * 4)),
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Subsignal("dq", Pins("_" * 32)),
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Subsignal("dqs_n", Pins("_" * 4)),
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Subsignal("dqs_p", Pins("_" * 4)),
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Subsignal("odt", Pins("_" * 1)),
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Subsignal("ras_n", Pins("_" * 1)),
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Subsignal("reset_n", Pins("_" * 1)),
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Subsignal("we_n", Pins("_" * 1)),
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Subsignal("vrn", Pins("_" * 1)),
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Subsignal("vrp", Pins("_" * 1)),
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),
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# I2C0 to Si5340 on Fast Servo
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("ps7_i2c", 0,
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Subsignal("sda", Pins("M2")),
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Subsignal("scl", Pins("M1")),
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IOStandard("LVCMOS18")
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),
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# Si540 nRST
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("nrst", 0, Pins("M7"), IOStandard("LVCMOS18")),
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]
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_connector_eem = [
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("eem", {
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"d0_cc_n": "C3",
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"d0_cc_p": "D3",
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"d1_n": "A4",
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"d1_p": "A5",
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"d2_n": "F6",
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"d2_p": "G6",
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"d3_n": "A6",
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"d3_p": "A7",
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"d4_n": "E5",
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"d4_p": "F5",
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"d5_n": "H3",
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"d5_p": "H4",
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"d6_n": "B8",
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"d6_p": "C8",
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"d7_n": "D8",
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"d7_p": "E8",
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}),
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]
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_connector_gpio = [
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("gpio", {
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"qspi_io3": "Y15",
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"qspi_io2": "AB14",
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"qspi_io1": "AB13",
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"qspi_io0": "V13",
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"qspi_clk": "V14",
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"qspi_ncs": "V15",
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"hrtim_che1": "U12",
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"hrtim_che2": "W13",
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"hrtim_cha1": "W12",
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"hrtim_cha2": "R17",
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"lptim2_out": "W15",
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"uart4_tx": "AB17",
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"spi1_mosi": "Y12",
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"spi1_miso": "Y13",
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"spi1_nss": "V16",
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"spi1_sck": "W16",
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"i2c1_sda": "AA17",
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"i2c1_scl": "Y17",
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})
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]
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# PS7 config ---------------------------------------------------------------------------------------
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ps7_config_board_preset = {
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"PCW_PRESET_BANK0_VOLTAGE" : "LVCMOS 3.3V",
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"PCW_PRESET_BANK1_VOLTAGE" : "LVCMOS 1.8V",
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"PCW_CRYSTAL_PERIPHERAL_FREQMHZ" : "33.333333",
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"PCW_QSPI_PERIPHERAL_ENABLE" : "1",
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"PCW_QSPI_GRP_SINGLE_SS_ENABLE" : "1",
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"PCW_SINGLE_QSPI_DATA_MODE" : "x4",
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"PCW_QSPI_QSPI_IO" : "MIO 1 .. 6",
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"PCW_QSPI_GRP_FBCLK_ENABLE" : "1",
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# SD Card
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"PCW_SD0_PERIPHERAL_ENABLE" : "1",
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"PCW_SD0_SD0_IO" : "MIO 40 .. 45",
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"PCW_MIO_40_PULLUP" : "disabled",
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"PCW_MIO_41_PULLUP" : "disabled",
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"PCW_MIO_42_PULLUP" : "disabled",
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"PCW_MIO_43_PULLUP" : "disabled",
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"PCW_MIO_44_PULLUP" : "disabled",
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"PCW_MIO_45_PULLUP" : "disabled",
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# UART
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"PCW_UART0_PERIPHERAL_ENABLE" : "1",
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"PCW_UART0_UART0_IO" : "MIO 10 .. 11",
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# ETHERNET
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"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" : "125",
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"PCW_ENET0_PERIPHERAL_CLKSRC" : "ARM PLL",
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"PCW_ENET0_PERIPHERAL_ENABLE" : "1",
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"PCW_ENET0_ENET0_IO" : "MIO 16 .. 27",
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"PCW_ENET0_GRP_MDIO_ENABLE" : "1",
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"PCW_ENET0_GRP_MDIO_IO" : "MIO 52 .. 53",
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"PCW_ENET_RESET_ENABLE" : "1",
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"PCW_ENET0_RESET_ENABLE" : "1",
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"PCW_ENET0_RESET_IO" : "MIO 50",
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# USB
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"PCW_USB0_PERIPHERAL_ENABLE" : "1",
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"PCW_USB0_USB0_IO" : "MIO 28 .. 39",
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"PCW_USB_RESET_ENABLE" : "1",
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"PCW_USB0_RESET_ENABLE" : "1",
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"PCW_USB0_RESET_IO" : "MIO 51",
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"PCW_WDT_PERIPHERAL_ENABLE" : "1",
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"PCW_TTC0_PERIPHERAL_ENABLE" : "1", # TTC0 required for Linux
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# I2C
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"PCW_I2C_RESET_ENABLE" : "0",
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"PCW_I2C_RESET_POLARITY" : "Active Low",
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# I2C0
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"PCW_I2C0_I2C0_IO" : "EMIO",
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"PCW_I2C0_PERIPHERAL_ENABLE" : "1",
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"PCW_I2C0_GRP_INT_ENABLE" : "1",
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"PCW_I2C0_GRP_INT_IO" : "EMIO",
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# I2C1
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"PCW_I2C1_PERIPHERAL_ENABLE" : "1",
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"PCW_I2C1_I2C1_IO" : "MIO 48 .. 49",
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"PCW_I2C1_I2C1_IO" : "MIO 12 .. 13",
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"PCW_I2C1_PERIPHERAL_ENABLE" : "1",
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"PCW_UIPARAM_DDR_MEMORY_TYPE" : "DDR 3 (Low Voltage)",
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"PCW_UIPARAM_DDR_PARTNO" : "MT41J256M16 RE-125",
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"PCW_GPIO_MIO_GPIO_ENABLE" : "1",
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"PCW_FPGA0_PERIPHERAL_FREQMHZ" : "100",
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"PCW_EN_CLK0_PORT" : "0", # dont use FCLK0
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}
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self):
|
||
|
|
XilinxPlatform.__init__(self, "xc7z015-clg485-1", _io, _connector_gpio + _connector_eem, toolchain="vivado")
|
||
|
|
ps7_config = ps7_config_board_preset
|
||
|
|
self.ps7_config = ps7_config
|
||
|
|
|
||
|
|
verilog_sources = os.listdir(verilog_dir)
|
||
|
|
self.add_sources(verilog_dir, *verilog_sources)
|
||
|
|
|
||
|
|
def do_finalize(self, fragment):
|
||
|
|
try:
|
||
|
|
XilinxPlatform.do_finalize(self, fragment)
|
||
|
|
self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
|
||
|
|
except ValueError:
|
||
|
|
pass
|
||
|
|
except ConstraintError:
|
||
|
|
pass
|