Sebastien Bourdeauducq fcc91513ec drop board-generated on ARTIQ 7 ... This is becoming too complicated, and with the number of systems increasing we should find a better way of managing bitstream builds anyway. Simply caching Verilog->bitfile does not cut it.		2021-09-12 18:35:26 +08:00
..
artiq.json	drop board-generated on ARTIQ 7	2021-09-12 18:35:26 +08:00
mcu.json	mcu: temporarily switch to pre-mqtt branch on harry's fork	2021-07-02 15:58:40 +08:00
web.json	hydra: use nixos 21.05 for web	2021-06-02 15:13:31 +08:00