Sebastien Bourdeauducq fcc91513ec drop board-generated on ARTIQ 7 ... This is becoming too complicated, and with the number of systems increasing we should find a better way of managing bitstream builds anyway. Simply caching Verilog->bitfile does not cut it.		2021-09-12 18:35:26 +08:00
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conda	riscv support in beta version (WIP)	2021-09-12 18:17:47 +08:00
conda-windows	allow Python 3.8 with conda	2021-07-05 20:42:18 +08:00
pkgs	riscv support in beta version (WIP)	2021-09-12 18:17:47 +08:00
windows	windows: fix conda eval errors	2021-09-12 18:23:39 +08:00
artiq-board.nix	drop board-generated on ARTIQ 7	2021-09-12 18:35:26 +08:00
default.nix	riscv support in beta version (WIP)	2021-09-12 18:17:47 +08:00
fetchcargo-legacy.nix	riscv support in beta version (WIP)	2021-09-12 18:17:47 +08:00
mozilla-overlay.nix	apply Mozilla nixpkgs overlay	2021-09-12 17:12:16 +08:00
shell-dev.nix	riscv support in beta version (WIP)	2021-09-12 18:17:47 +08:00
shell.nix	rename jobsets to artiq-fast/artiq-full	2019-07-17 19:19:43 +08:00
vivado.nix	vivado: update to 2020.1	2020-06-11 13:23:15 +08:00
wfvm-legacy.nix	keep old WFVM/conda for ARTIQ legacy	2021-07-05 20:34:18 +08:00
wfvm.nix	wfvm: update	2021-09-09 20:50:53 +08:00