With the Nix model it is relatively straightforward to reuse and cache artifacts between builds (in particular the bitstream, which is slow to compile):
split the gateware version tagging into a separate step that modifies the .bit and takes little time. That probably needs some modifications to the identifier gateware core, plus something like ISE's Data2BRAM.
have Nix manage fine-grained build steps (instead of just running the ARTIQ target script that does everything) and make Nix aware of the precise inputs of each step.
With the Nix model it is relatively straightforward to reuse and cache artifacts between builds (in particular the bitstream, which is slow to compile):
1. split the gateware version tagging into a separate step that modifies the .bit and takes little time. That probably needs some modifications to the identifier gateware core, plus something like ISE's Data2BRAM.
2. have Nix manage fine-grained build steps (instead of just running the ARTIQ target script that does everything) and make Nix aware of the precise inputs of each step.
I've found a way to accomplish this in the Nix part of the build. I'm going to prepare a Merge Request for review once I'm done testing (these runs take long).
I have yet to find the version info in the bitstream sources.
I've found a way to accomplish this in the Nix part of the build. I'm going to prepare a Merge Request for review once I'm done testing (these runs take long).
I have yet to find the version info in the bitstream sources.
The version info is in the "identifier" core from MiSoC.
You will have to change it to use BRAM since I suspect that the current code that may produce combinatorial logic with LUTs will be difficult to edit post-compilation.
The version info is in the "identifier" core from MiSoC.
You will have to change it to use BRAM since I suspect that the current code that may produce combinatorial logic with LUTs will be difficult to edit post-compilation.
get_cells identifier_str
WARNING:[Vivado12-180] No cells matched 'identifier_str'.
This returns some cells but none looks like having to do with the ident:
get_cells-hierarchical *-filter {INIT_38=~*}
Are these TCL commands still supposed to work?
```tcl
get_cells identifier_str
WARNING: [Vivado 12-180] No cells matched 'identifier_str'.
```
This returns some cells but none looks like having to do with the ident:
```tcl
get_cells -hierarchical * -filter {INIT_38=~*}
```
See the next commit 4a8d361ace.
The memory is now made up of eight ROM256X1 called identifier_str0 ... identifier_str7.
See the next commit https://github.com/m-labs/artiq/commit/4a8d361acebf1e6b45e9fe35201315798b02d2f3.
The memory is now made up of eight ROM256X1 called ```identifier_str0``` ... ```identifier_str7```.
With the Nix model it is relatively straightforward to reuse and cache artifacts between builds (in particular the bitstream, which is slow to compile):
I've found a way to accomplish this in the Nix part of the build. I'm going to prepare a Merge Request for review once I'm done testing (these runs take long).
I have yet to find the version info in the bitstream sources.
The version info is in the "identifier" core from MiSoC.
You will have to change it to use BRAM since I suspect that the current code that may produce combinatorial logic with LUTs will be difficult to edit post-compilation.
Since
9e66dd7075the identifier can be rewritten without rebuilding the whole gateware.Run
vivado -mode tcland then:The new identifier string appears in the log:
NB: I have not tried using more optimal primitives (e.g. ROM256X1).
Ok, it also works with ROM256X1 :)
Are these TCL commands still supposed to work?
This returns some cells but none looks like having to do with the ident:
See the next commit
4a8d361ace.The memory is now made up of eight ROM256X1 called
identifier_str0...identifier_str7.Ok, in my case they were optimized away with
.INIT(32'd0).Using
32'hAAAAAAAAkeeps that from happening.