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14
gluelogic/default.nix
View File

@ -58,12 +58,12 @@ in
src = <mirnySrc>;
};
mirny-cpld-release = buildMirnyCpld rec {
version = "0.3.1";
version = "0.3";
src = pkgs.fetchFromGitHub {
owner = "quartiq";
repo = "mirny";
rev = "v${version}";
sha256 = "sha256-FbPUgXcUByEnczbnDCh8wYPO+rpSZSAabG1rtvA7mIs=";
sha256 = "sha256-u1iXcbGX6JkVgfpnCbkyTOVoMYnYcSufLBb6OBAeu8c=";
};
};
mirny-cpld-legacy-almazny = buildMirnyCpld rec {
@ -76,6 +76,16 @@ in
};
patchPhase = "patch -p1 < ${./mirny-legacy-almazny.diff}";
};
mirny-cpld-almazny = buildMirnyCpld rec {
version = "0.3";
src = pkgs.fetchFromGitHub {
owner = "quartiq";
repo = "mirny";
rev = "v${version}";
sha256 = "sha256-u1iXcbGX6JkVgfpnCbkyTOVoMYnYcSufLBb6OBAeu8c=";
};
patchPhase = "patch -p1 < ${./mirny-almazny.diff}";
};
fastino-fpga = pkgs.stdenv.mkDerivation {
name = "fastino-fpga";
src = <fastinoSrc>;

40
gluelogic/mirny-almazny.diff Normal file
View File

@ -0,0 +1,40 @@
diff --git a/mirny.py b/mirny.py
index 6c041de..73991b1 100644
--- a/mirny.py
+++ b/mirny.py
@@ -135,7 +135,7 @@ class SR(Module):
)
]
- def connect_ext(self, ext, adr, mask):
+ def connect_ext(self, ext, adr, mask, sdi_passthrough=False):
adr &= mask
self._check_intersection(adr, mask)
self._slaves.append((ext, adr, mask))
@@ -146,12 +146,16 @@ class SR(Module):
stb.ce.eq(self.bus.re),
# don't glitch with &stb.o
ext.sck.eq(self.ext.sck),
- ext.sdi.eq(self.ext.sdi & stb.o),
ext.cs.eq(stb.o),
If(stb.o,
self.ext.sdo.eq(ext.sdo),
),
]
+ # Almazny shares one SDI with 4 devices, it cannot be masked by stb
+ if sdi_passthrough:
+ self.comb += ext.sdi.eq(self.ext.sdi)
+ else:
+ self.comb += ext.sdi.eq(self.ext.sdi & stb.o),
def intersection(a, b):
@@ -360,7 +364,7 @@ class Mirny(Module):
]
ext = Record(ext_layout)
- self.sr.connect_ext(ext, adr=i + 12, mask=mask)
+ self.sr.connect_ext(ext, adr=i + 12, mask=mask, sdi_passthrough=True)
self.comb += [
mezz[i + 3].oe.eq(1),
mezz[i + 3].o.eq(~ext.cs), # Almazny REG_LATCH

6
hydra/artiq.json
View File

@ -147,9 +147,9 @@
"emailoverride": "",
"keepnr": 50,
"inputs": {
"nixpkgs": { "type": "git", "value": "https://github.com/NixOS/nixpkgs.git nixos-24.11", "emailresponsible": false },
"nixpkgs": { "type": "git", "value": "https://github.com/NixOS/nixpkgs.git nixos-24.05", "emailresponsible": false },
"nixScripts": { "type": "git", "value": "https://git.m-labs.hk/M-Labs/nix-scripts.git", "emailresponsible": false },
"urukulSrc": { "type": "git", "value": "https://git.m-labs.hk/M-Labs/urukul-pld.git", "emailresponsible": false },
"urukulSrc": { "type": "git", "value": "https://github.com/quartiq/urukul.git", "emailresponsible": false },
"mirnySrc": { "type": "git", "value": "https://github.com/quartiq/mirny.git", "emailresponsible": false },
"fastinoSrc": { "type": "git", "value": "https://github.com/quartiq/fastino.git", "emailresponsible": false },
"phaserSrc": { "type": "git", "value": "https://github.com/quartiq/phaser.git", "emailresponsible": false }
@ -161,7 +161,7 @@
"type": 1,
"hidden": false,
"description": "Simple Python Communications",
"flake": "git+https://github.com/m-labs/sipyco.git",
"flake": "github:m-labs/sipyco",
"checkinterval": 600,
"schedulingshares": 10,
"enableemail": false,

5
hydra/mcu.json
View File

@ -11,10 +11,11 @@
"emailoverride": "",
"keepnr": 10,
"inputs": {
"nixpkgs": { "type": "git", "value": "https://github.com/NixOS/nixpkgs.git nixos-24.11", "emailresponsible": false },
"nixpkgs": { "type": "git", "value": "https://github.com/NixOS/nixpkgs.git nixos-24.05", "emailresponsible": false },
"mozillaOverlay": { "type": "git", "value": "https://github.com/mozilla/nixpkgs-mozilla.git", "emailresponsible": false },
"nixScripts": { "type": "git", "value": "https://git.m-labs.hk/M-Labs/nix-scripts.git", "emailresponsible": false },
"stabilizerSrc": { "type": "git", "value": "https://github.com/quartiq/stabilizer.git main", "emailresponsible": false }
"stabilizerSrc": { "type": "git", "value": "https://github.com/quartiq/stabilizer.git main", "emailresponsible": false },
"saymaMmcSrc": { "type": "git", "value": "https://github.com/sinara-hw/openMMC.git sayma-devel", "emailresponsible": false }
}
},
"thermostat": {

2
hydra/web.json
View File

@ -11,7 +11,7 @@
"emailoverride": "",
"keepnr": 10,
"inputs": {
"nixpkgs": { "type": "git", "value": "https://github.com/NixOS/nixpkgs.git nixos-24.11", "emailresponsible": false },
"nixpkgs": { "type": "git", "value": "https://github.com/NixOS/nixpkgs.git nixos-24.05", "emailresponsible": false },
"nixScripts": { "type": "git", "value": "https://git.m-labs.hk/M-Labs/nix-scripts.git", "emailresponsible": false },
"webSrc": { "type": "git", "value": "https://git.m-labs.hk/M-Labs/web2019.git", "emailresponsible": false },
"nmigenSrc": { "type": "git", "value": "https://gitlab.com/nmigen/nmigen.git", "emailresponsible": false }

48
mcu-contrib/default.nix
View File

@ -8,8 +8,8 @@ let
"thumbv7em-none-eabihf"
];
rustManifest = pkgs.fetchurl {
url = "https://static.rust-lang.org/dist/2024-11-28/channel-rust-stable.toml";
sha256 = "b3544fb72bc3189697fc18ac2d3fa27d57ee8434f59d9919d4d70af2c6f010b3";
url = "https://static.rust-lang.org/dist/2024-06-13/channel-rust-stable.toml";
sha256 = "sha256-Ngiz76YP4HTY75GGdH2P+APE/DEIx2R/Dn+BwwOyzZU=";
};
rustChannelOfTargets = _channel: _date: targets:
(pkgs.lib.rustLib.fromManifestFile rustManifest {
@ -20,21 +20,16 @@ let
};
rust = rustChannelOfTargets "nightly" null targets;
rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
rustc = rust // {
# https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
targetPlatforms = pkgs.lib.platforms.all;
tier1TargetPlatforms = pkgs.lib.platforms.all;
badTargetPlatforms = [ ];
};
rustc = rust;
cargo = rust;
});
buildStm32Firmware = { name, src, cargoDepsName ? name, patchPhase ? "", extraNativeBuildInputs ? [], checkPhase ? "", doCheck ? true, binaryName ? name, extraCargoBuildArgs ? "", outputHashes ? {} }:
buildStm32Firmware = { name, src, cargoDepsName ? name, cargoPatches ? [], patchPhase ? "", extraNativeBuildInputs ? [], checkPhase ? "", doCheck ? true, binaryName ? name, extraCargoBuildArgs ? "", outputHashes ? {} }:
rustPlatform.buildRustPackage rec {
inherit name cargoDepsName;
version = "0.0.0";
inherit src;
inherit src cargoPatches;
cargoLock = { lockFile = "${src}/Cargo.lock"; inherit outputHashes; };
@ -71,11 +66,10 @@ in
patchPhase = ''
patch -p1 < ${./pounder-725.diff}
'';
cargoPatches = [
./pounder-cargo-patch.diff
];
doCheck = false;
outputHashes = {
"miniconf-0.18.0" = "sha256-LNlJkQoHK0ukwdekKtt1zg3JLD5CQnq6GQtvw42+FfA=";
"idsp-0.17.0" = "sha256-wVROBoWbD1k1bW+C4p0zngbiMkhdPLiLK91ggWivYqs=";
};
} // value))) {
dual-iir = {};
dual-iir-pounder_v1_0 = {
@ -83,4 +77,28 @@ in
extraCargoBuildArgs = "--features pounder_v1_0";
};
lockin = {};
}
} //
{
# openMMC build system breaks if host compiler is not available, so do not use stdenvNoCC here
sayma-mmc = pkgs.stdenv.mkDerivation {
name = "sayma-mmc";
src = <saymaMmcSrc>;
phases = [ "unpackPhase" "buildPhase" "installPhase" ];
nativeBuildInputs = [ pkgs.cmake pkgs.gcc-arm-embedded ];
buildPhase =
''
mkdir build
cd build
cmake .. -DBOARD=sayma -DBOARD_RTM=sayma -DVERSION= -DTARGET_CONTROLLER=LPC1776 -DCMAKE_BUILD_TYPE=Debug
make
'';
installPhase =
''
mkdir $out
cp out/* $out
mkdir -p $out $out/nix-support
echo file binary-dist $out/openMMC.axf >> $out/nix-support/hydra-build-products
echo file binary-dist $out/openMMC.bin >> $out/nix-support/hydra-build-products
'';
};
}

560
mcu-contrib/pounder-725.diff
View File

@ -1,11 +1,11 @@
diff --git a/ad9959/src/lib.rs b/ad9959/src/lib.rs
index bb66ddc4..f72a36b1 100644
index 025f7d4f..59578cce 100644
--- a/ad9959/src/lib.rs
+++ b/ad9959/src/lib.rs
@@ -2,8 +2,24 @@
use arbitrary_int::{u10, u14, u2, u24, u3, u4, u5, Number};
use bitbybit::{bitenum, bitfield};
use bit_field::BitField;
use bitflags::bitflags;
+use core::ops::Range;
use embedded_hal::{blocking::delay::DelayUs, digital::v2::OutputPin};
@ -24,19 +24,49 @@ index bb66ddc4..f72a36b1 100644
+ end: 160e6,
+};
+
/// A trait that allows a HAL to provide a means of communicating with the AD9959.
pub trait Interface {
type Error;
@@ -234,7 +250,7 @@ impl<I: Interface> Ad9959<I> {
///
/// Returns:
/// The actual frequency configured for the internal system clock.
- fn set_system_clock(
+ pub fn set_system_clock(
&mut self,
/// A device driver for the AD9959 direct digital synthesis (DDS) chip.
///
/// This chip provides four independently controllable digital-to-analog output sinusoids with
@@ -218,23 +234,17 @@ impl<I: Interface> Ad9959<I> {
reference_clock_frequency: f32,
multiplier: u5,
@@ -485,6 +501,109 @@ impl<I: Interface> Ad9959<I> {
multiplier: u8,
) -> Result<f32, Error> {
+ let frequency =
+ validate_clocking(reference_clock_frequency, multiplier)?;
self.reference_clock_frequency = reference_clock_frequency;
- if multiplier != 1 && !(4..=20).contains(&multiplier) {
- return Err(Error::Bounds);
- }
-
- let frequency = multiplier as f32 * self.reference_clock_frequency;
- if frequency > 500_000_000.0f32 {
- return Err(Error::Frequency);
- }
-
// TODO: Update / disable any enabled channels?
let mut fr1: [u8; 3] = [0, 0, 0];
self.read(Register::FR1, &mut fr1)?;
fr1[0].set_bits(2..=6, multiplier);
- let vco_range = frequency > 255e6;
+ let vco_range = HIGH_GAIN_VCO_RANGE.contains(&frequency)
+ || frequency == HIGH_GAIN_VCO_RANGE.end;
fr1[0].set_bit(7, vco_range);
self.write(Register::FR1, &fr1)?;
@@ -365,9 +375,7 @@ impl<I: Interface> Ad9959<I> {
channel: Channel,
phase_turns: f32,
) -> Result<f32, Error> {
- let phase_offset: u16 =
- (phase_turns * (1 << 14) as f32) as u16 & 0x3FFFu16;
-
+ let phase_offset = phase_to_pow(phase_turns)?;
self.modify_channel(
channel,
Register::CPOW0,
@@ -513,6 +521,108 @@ impl<I: Interface> Ad9959<I> {
}
}
@ -135,42 +165,74 @@ index bb66ddc4..f72a36b1 100644
+ return Err(Error::Bounds);
+ }
+
+ let asf = (amplitude * (1 << 10) as f32) as u16;
+ let acr = match u10::try_new(asf) {
+ Ok(asf) => Acr::default().with_multiplier(true).with_asf(asf),
+ Err(_) => Acr::default().with_multiplier(false),
+ };
+ Ok(acr.raw_value().into())
+ let acr: u32 = *0u32
+ .set_bits(0..=9, ((amplitude * (1 << 10) as f32) as u32) & 0x3FF)
+ .set_bit(12, amplitude != 1.0);
+
+ Ok(acr as u32)
+}
+
/// Represents a means of serializing a DDS profile for writing to a stream.
pub struct ProfileSerializer {
mode: Mode,
// heapless::Vec<u8, 32>, especially its extend_from_slice() is slow
@@ -568,6 +678,39 @@ impl ProfileSerializer {
}
}
+ /// Update the system clock configuration.
+ ///
+ /// # Args
+ /// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core.
+ /// * `multiplier` - The frequency multiplier of the system clock. Must be 1 or 4-20.
+ ///
+ /// # Limitations
+ /// The correctness of the FR1 register setting code rely on FR1\[0:17\] staying 0.
+ pub fn set_system_clock(
+ &mut self,
+ reference_clock_frequency: f32,
+ multiplier: u8,
+ ) -> Result<f32, Error> {
+ let frequency = reference_clock_frequency * multiplier as f32;
+
+ // The enabled channel will be updated after clock reconfig
+ let mut fr1 = [0u8; 3];
+
+ // The ad9959 crate does not modify FR1[0:17]. These bits keep their default value.
+ // These bits by default are 0.
+ // Reading the register then update is not possible to implement in a serializer, where
+ // many QSPI writes are performed in burst. Switching between read and write requires
+ // breaking the QSPI indirect write mode and switch into the QSPI indirect read mode.
+ fr1[0].set_bits(2..=6, multiplier);
+
+ // Frequencies within the VCO forbidden range (160e6, 255e6) are already rejected.
+ let vco_range = HIGH_GAIN_VCO_RANGE.contains(&frequency);
+ fr1[0].set_bit(7, vco_range);
+
+ self.add_write(Register::FR1, &fr1);
+ Ok(frequency)
+ }
+
/// Add a register write to the serialization data.
fn add_write(&mut self, register: Register, value: &[u8]) {
let data = &mut self.data[self.index..];
diff --git a/src/bin/dual-iir.rs b/src/bin/dual-iir.rs
index e7596341..71eee420 100644
index a4a04be8..83dcdefb 100644
--- a/src/bin/dual-iir.rs
+++ b/src/bin/dual-iir.rs
@@ -28,6 +28,7 @@
#![no_std]
#![no_main]
+use core::mem::{MaybeUninit, size_of};
use core::sync::atomic::{fence, Ordering};
use miniconf::{Leaf, StrLeaf, Tree};
@@ -46,6 +47,8 @@ use stabilizer::{
@@ -47,6 +47,8 @@ use stabilizer::{
dac::{Dac0Output, Dac1Output, DacCode},
hal,
signal_generator::{self, Source},
signal_generator::{self, SignalGenerator},
+ pounder::{ClockConfig, PounderConfig},
+ setup::PounderDevices as Pounder,
timers::SamplingTimer,
DigitalInput0, DigitalInput1, Pgia, SerialTerminal, SystemTimer,
Systick, UsbDevice,
@@ -194,6 +197,15 @@ pub struct DualIir {
///
/// Can be multicast.
stream: Leaf<StreamTarget>,
DigitalInput0, DigitalInput1, SerialTerminal, SystemTimer, Systick,
UsbDevice, AFE0, AFE1,
@@ -179,6 +181,16 @@ pub struct DualIir {
/// See [signal_generator::BasicConfig#miniconf]
#[tree(depth = 2)]
signal_generator: [signal_generator::BasicConfig; 2],
+
+ /// Specifies the config for pounder DDS clock configuration, DDS channels & attenuations
+ ///
+ /// # Path
@ -182,41 +244,42 @@ index e7596341..71eee420 100644
+ pounder: Option<PounderConfig>,
}
impl DualIir {
@@ -215,6 +227,7 @@ impl Default for DualIir {
_trigger: Leaf(()),
stream: Default::default(),
ch: Default::default(),
impl Default for DualIir {
@@ -206,6 +218,8 @@ impl Default for DualIir {
signal_generator: [signal_generator::BasicConfig::default(); 2],
stream_target: StreamTarget::default(),
+
+ pounder: None.into(),
}
}
}
@@ -238,6 +251,7 @@ mod app {
settings: Settings,
active: [Active; 2],
@@ -222,6 +236,7 @@ mod app {
active_settings: DualIir,
telemetry: TelemetryBuffer,
signal_generator: [SignalGenerator; 2],
+ pounder: Option<Pounder>,
}
#[local]
@@ -248,6 +262,7 @@ mod app {
afes: [Pgia; 2],
@@ -233,6 +248,7 @@ mod app {
adcs: (Adc0Input, Adc1Input),
dacs: (Dac0Output, Dac1Output),
iir_state: [[[f32; 4]; IIR_CASCADE_LENGTH]; 2],
+ dds_clock_state: Option<ClockConfig>,
generator: FrameGenerator,
cpu_temp_sensor: stabilizer::hardware::cpu_temp_sensor::CpuTempSensor,
}
@@ -257,7 +272,7 @@ mod app {
@@ -242,7 +258,7 @@ mod app {
let clock = SystemTimer::new(|| Systick::now().ticks());
// Configure the microcontroller
- let (stabilizer, _pounder) = hardware::setup::setup::<Settings, 9>(
+ let (mut stabilizer, pounder) = hardware::setup::setup::<Settings, 9>(
- let (stabilizer, _pounder) = hardware::setup::setup::<Settings, 4>(
+ let (mut stabilizer, pounder) = hardware::setup::setup::<Settings, 4>(
c.core,
c.device,
clock,
@@ -276,6 +291,13 @@ mod app {
@@ -261,6 +277,13 @@ mod app {
let generator = network.configure_streaming(StreamFormat::AdcDacData);
@ -230,50 +293,50 @@ index e7596341..71eee420 100644
let shared = Shared {
usb: stabilizer.usb,
network,
@@ -287,6 +309,7 @@ mod app {
.map(|a| a.build().unwrap()),
telemetry: TelemetryBuffer::default(),
@@ -279,6 +302,7 @@ mod app {
),
],
settings: stabilizer.settings,
+ pounder
};
let mut local = Local {
@@ -296,6 +319,7 @@ mod app {
afes: stabilizer.afes,
@@ -289,6 +313,7 @@ mod app {
adcs: stabilizer.adcs,
dacs: stabilizer.dacs,
iir_state: [[[0.; 4]; IIR_CASCADE_LENGTH]; 2],
+ dds_clock_state,
generator,
cpu_temp_sensor: stabilizer.temperature_sensor,
};
@@ -448,7 +472,7 @@ mod app {
@@ -458,7 +483,7 @@ mod app {
}
}
- #[task(priority = 1, local=[afes], shared=[network, settings, active])]
+ #[task(priority = 1, local=[afes, dds_clock_state], shared=[network, settings, active, pounder])]
- #[task(priority = 1, local=[afes], shared=[network, settings, active_settings, signal_generator])]
+ #[task(priority = 1, local=[afes, dds_clock_state], shared=[network, settings, active_settings, signal_generator, pounder])]
async fn settings_update(mut c: settings_update::Context) {
c.shared.settings.lock(|settings| {
c.local.afes[0].set_gain(*settings.dual_iir.ch[0].gain);
@@ -490,31 +514,49 @@ mod app {
(a.run, a.biquad) = b;
c.local.afes.0.set_gain(settings.dual_iir.afe[0]);
@@ -482,6 +507,17 @@ mod app {
),
}
});
+ // Update Pounder configurations
+ c.shared.pounder.lock(|pounder| {
+ if let Some(pounder) = pounder {
+ let pounder_settings = settings.dual_iir.pounder.as_ref().unwrap();
+ // let mut clocking = c.local.dds_clock_state;
+ pounder.update_dds(
+ *pounder_settings,
+ c.local.dds_clock_state.as_mut().unwrap(),
+ );
+ }
+ });
+
c.shared
.network
.lock(|net| net.direct_stream(*settings.dual_iir.stream));
}
+ // Update Pounder configurations
+ c.shared.pounder.lock(|pounder| {
+ if let Some(pounder) = pounder {
+ let pounder_settings = settings.dual_iir.pounder.as_ref().unwrap();
+ // let mut clocking = c.local.dds_clock_state;
+ pounder.update_dds(
+ *pounder_settings,
+ c.local.dds_clock_state.as_mut().unwrap(),
+ );
+ }
+ });
let target = settings.dual_iir.stream_target.into();
c.shared.network.lock(|net| net.direct_stream(target));
@@ -492,22 +528,31 @@ mod app {
});
}
@ -281,17 +344,18 @@ index e7596341..71eee420 100644
+ #[task(priority = 1, shared=[network, settings, telemetry, pounder], local=[cpu_temp_sensor])]
async fn telemetry(mut c: telemetry::Context) {
loop {
let telemetry =
c.shared.telemetry.lock(|telemetry| telemetry.clone());
let telemetry: TelemetryBuffer =
c.shared.telemetry.lock(|telemetry| *telemetry);
- let (gains, telemetry_period) =
+ let (gains, telemetry_period, pounder_config) =
c.shared.settings.lock(|settings| {
(
settings.dual_iir.ch.each_ref().map(|ch| *ch.gain),
*settings.dual_iir.telemetry_period,
- (settings.dual_iir.afe, settings.dual_iir.telemetry_period)
+ (
+ settings.dual_iir.afe,
+ settings.dual_iir.telemetry_period,
+ settings.dual_iir.pounder
)
+ )
});
+ let pounder_telemetry = c.shared.pounder.lock(|pounder| {
@ -308,86 +372,17 @@ index e7596341..71eee420 100644
});
diff --git a/src/bin/lockin.rs b/src/bin/lockin.rs
index 064b43d3..fd0c959e 100644
index e0cfb58f..c9b26831 100644
--- a/src/bin/lockin.rs
+++ b/src/bin/lockin.rs
@@ -28,9 +28,10 @@
#![no_main]
use core::{
- iter,
- mem::MaybeUninit,
+ convert::TryFrom,
+ mem::{MaybeUninit, size_of},
sync::atomic::{fence, Ordering},
+ iter
};
use miniconf::{Leaf, Tree};
@@ -246,7 +247,7 @@ mod app {
#[shared]
struct Shared {
usb: UsbDevice,
- network: NetworkUsers<Lockin, 2>,
+ network: NetworkUsers<Lockin, 6>,
settings: Settings,
active_settings: Lockin,
telemetry: TelemetryBuffer,
@@ -254,7 +255,7 @@ mod app {
#[local]
struct Local {
- usb_terminal: SerialTerminal<Settings, 3>,
+ usb_terminal: SerialTerminal<Settings, 6>,
sampling_timer: SamplingTimer,
digital_inputs: (DigitalInput0, DigitalInput1),
timestamper: InputStamper,
@@ -273,7 +274,7 @@ mod app {
let clock = SystemTimer::new(|| Systick::now().ticks());
// Configure the microcontroller
- let (mut stabilizer, _pounder) = hardware::setup::setup::<Settings, 3>(
+ let (mut stabilizer, _pounder) = hardware::setup::setup::<Settings, 6>(
c.core,
c.device,
clock,
@@ -535,6 +536,7 @@ mod app {
*gains[0],
*gains[1],
@@ -551,6 +551,7 @@ mod app {
gains[0],
gains[1],
c.local.cpu_temp_sensor.get_temperature().unwrap(),
+ None,
))
});
diff --git a/src/bin/urukul.rs b/src/bin/urukul.rs
index fc7faf40..10ff9016 100644
--- a/src/bin/urukul.rs
+++ b/src/bin/urukul.rs
@@ -104,21 +104,21 @@ mod app {
#[shared]
struct Shared {
usb: UsbDevice,
- network: NetworkUsers<App, 3>,
+ network: NetworkUsers<App, 6>,
settings: Settings,
}
#[local]
struct Local {
urukul: Urukul,
- usb_terminal: SerialTerminal<Settings, 4>,
+ usb_terminal: SerialTerminal<Settings, 6>,
}
#[init]
fn init(c: init::Context) -> (Shared, Local) {
let clock = SystemTimer::new(|| Systick::now().ticks());
- let (stabilizer, _pounder) = hardware::setup::setup::<Settings, 4>(
+ let (stabilizer, _pounder) = hardware::setup::setup::<Settings, 6>(
c.core,
c.device,
clock,
diff --git a/src/hardware/pounder/attenuators.rs b/src/hardware/pounder/attenuators.rs
index cfd08b7f..2570f506 100644
--- a/src/hardware/pounder/attenuators.rs
@ -417,81 +412,22 @@ index cfd08b7f..2570f506 100644
Ok(attenuation_code as f32 / 2.0)
}
diff --git a/src/hardware/pounder/dds_output.rs b/src/hardware/pounder/dds_output.rs
index 41fb7762..9404894f 100644
index 3ae1ce90..cd978b01 100644
--- a/src/hardware/pounder/dds_output.rs
+++ b/src/hardware/pounder/dds_output.rs
@@ -55,8 +55,9 @@
@@ -55,7 +55,7 @@
use log::warn;
use stm32h7xx_hal as hal;
-use super::{hrtimer::HighResTimerE, QspiInterface};
-use ad9959::{Mode, ProfileSerializer};
+use arbitrary_int::{u14, u24};
+use super::{hrtimer::HighResTimerE, Profile, QspiInterface};
+use ad9959::{Acr, Channel, Mode, ProfileSerializer};
use ad9959::{Channel, Mode, ProfileSerializer};
/// The DDS profile update stream.
pub struct DdsOutput {
@@ -91,8 +92,9 @@ impl DdsOutput {
@@ -157,6 +157,46 @@ impl<'a> ProfileBuilder<'a> {
self
}
/// Get a builder for serializing a Pounder DDS profile.
- pub fn builder(&mut self) -> ProfileSerializer {
- ProfileSerializer::new(self.mode)
+ pub fn builder(&mut self) -> ProfileBuilder {
+ let mode = self.mode;
+ ProfileBuilder {dds_output: self, serializer: ProfileSerializer::new(mode)}
}
/// Write a profile to the stream.
@@ -105,7 +107,7 @@ impl DdsOutput {
/// # Args
/// * `profile` - The serialized DDS profile to write.
#[inline]
- pub fn write(&mut self, mut profile: ProfileSerializer) {
+ pub fn write(&mut self, profile: &mut ProfileSerializer) {
// Note(unsafe): We own the QSPI interface, so it is safe to access the registers in a raw
// fashion.
let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
@@ -124,3 +126,69 @@ impl DdsOutput {
self.io_update_trigger.trigger();
}
}
+
+/// A temporary builder for serializing and writing profiles.
+pub struct ProfileBuilder<'a> {
+ dds_output: &'a mut DdsOutput,
+ serializer: ProfileSerializer,
+}
+
+impl ProfileBuilder<'_> {
+ /// Update a number of channels with the provided configuration
+ ///
+ /// # Args
+ /// * `channels` - A list of channels to apply the configuration to.
+ /// * `ftw` - If provided, indicates a frequency tuning word for the channels.
+ /// * `pow` - If provided, indicates a phase offset word for the channels.
+ /// * `acr` - If provided, indicates the amplitude control register for the channels. The
+ /// 24-bits of the ACR should be stored in the last 3 LSB.
+ #[allow(dead_code)]
+ #[inline]
+ pub fn update_channels(
+ &mut self,
+ channels: Channel,
+ ftw: Option<u32>,
+ pow: Option<u16>,
+ acr: Option<u32>,
+ ) -> &mut Self {
+ let pow = if let Some(pow) = pow {
+ Some(u14::try_new(pow & 0x3FFF).unwrap())
+ } else { None };
+ let acr = if let Some(acr) = acr {
+ Some(Acr::new_with_raw_value(u24::try_new(acr).unwrap()))
+ } else { None };
+ self.serializer.push(channels, ftw, pow, acr);
+ self
+ }
+
+ /// Update a number of channels with fully defined profile settings.
+ ///
+ /// # Args
@ -507,60 +443,70 @@ index 41fb7762..9404894f 100644
+ channels: Channel,
+ profile: Profile,
+ ) -> &mut Self {
+ self.serializer.push(
+ self.serializer.update_channels(
+ channels,
+ Some(profile.frequency_tuning_word),
+ Some(u14::try_new(profile.phase_offset & 0x3FFF).unwrap()),
+ Some(Acr::new_with_raw_value(u24::try_new(profile.amplitude_control).unwrap())),
+ Some(profile.phase_offset),
+ Some(profile.amplitude_control),
+ );
+ self
+ }
+
+ /// Write the profile to the DDS asynchronously.
+ #[allow(dead_code)]
+ /// Update the system clock configuration.
+ ///
+ /// # Args
+ /// * `reference_clock_frequency` - The reference clock frequency provided to the AD9959 core.
+ /// * `multiplier` - The frequency multiplier of the system clock. Must be 1 or 4-20.
+ #[inline]
+ pub fn write(&mut self) {
+ self.dds_output.write(&mut self.serializer);
+ pub fn set_system_clock(
+ &mut self,
+ reference_clock_frequency: f32,
+ multiplier: u8,
+ ) -> Result<&mut Self, ad9959::Error> {
+ self.serializer
+ .set_system_clock(reference_clock_frequency, multiplier)?;
+ Ok(self)
+ }
+}
+
/// Write the profile to the DDS asynchronously.
#[allow(dead_code)]
#[inline]
diff --git a/src/hardware/pounder/mod.rs b/src/hardware/pounder/mod.rs
index 8cf1fb5c..8cc99423 100644
index 5bc7e9ff..5b8d5d30 100644
--- a/src/hardware/pounder/mod.rs
+++ b/src/hardware/pounder/mod.rs
@@ -1,12 +1,15 @@
@@ -1,10 +1,17 @@
use self::attenuators::AttenuatorInterface;
use super::hal;
-use crate::hardware::{shared_adc::AdcChannel, I2c1Proxy};
-use ad9959::Address;
-use bitbybit::bitenum;
+use crate::hardware::{setup, shared_adc::AdcChannel, I2c1Proxy};
+use crate::net::telemetry::PounderTelemetry;
+use ad9959::{Address, frequency_to_ftw, phase_to_pow, amplitude_to_acr, validate_clocking};
use embedded_hal_02::blocking::spi::Transfer;
+use miniconf::{Leaf, Tree};
+use ad9959::{
+ amplitude_to_acr, frequency_to_ftw, phase_to_pow, validate_clocking,
+};
use embedded_hal::blocking::spi::Transfer;
use enum_iterator::Sequence;
+use miniconf::Tree;
+use rf_power::PowerMeasurementInterface;
use serde::{Deserialize, Serialize};
use strum::IntoEnumIterator;
+use stm32h7xx_hal::time::MegaHertz;
pub mod attenuators;
pub mod dds_output;
@@ -122,38 +125,97 @@ impl From<Channel> for GpioPin {
@@ -120,40 +127,99 @@ impl From<Channel> for GpioPin {
}
}
-#[derive(Serialize, Deserialize, Copy, Clone, Debug)]
-pub struct DdsChannelState {
- pub phase_offset: f32,
- pub frequency: f32,
- pub amplitude: f32,
- pub enabled: bool,
+#[derive(Serialize, Deserialize, Copy, Clone, Debug, Tree)]
+pub struct DdsChannelConfig {
+ pub frequency: Leaf<f32>,
+ pub phase_offset: Leaf<f32>,
+ pub amplitude: Leaf<f32>,
pub frequency: f32,
+ pub phase_offset: f32,
pub amplitude: f32,
- pub enabled: bool,
}
-#[derive(Serialize, Deserialize, Copy, Clone, Debug)]
@ -570,9 +516,9 @@ index 8cf1fb5c..8cc99423 100644
+impl Default for DdsChannelConfig {
+ fn default() -> Self {
+ Self {
+ frequency: 0.0.into(),
+ phase_offset: 0.0.into(),
+ amplitude: 0.0.into(),
+ frequency: 0.0,
+ phase_offset: 0.0,
+ amplitude: 0.0,
+ }
+ }
}
@ -594,12 +540,8 @@ index 8cf1fb5c..8cc99423 100644
+ /// Control amplitudes of DDS channels. It corresponds to the AD9959 ACR register, which
+ /// controls the amplitude scaling factor of DDS channels.
+ pub amplitude_control: u32,
}
-#[derive(Serialize, Deserialize, Copy, Clone, Debug)]
-pub struct OutputChannelState {
- pub attenuation: f32,
- pub channel: DdsChannelState,
+}
+
+impl TryFrom<(ClockConfig, ChannelConfig)> for Profile {
+ type Error = ad9959::Error;
+
@ -607,52 +549,52 @@ index 8cf1fb5c..8cc99423 100644
+ (clocking, channel): (ClockConfig, ChannelConfig),
+ ) -> Result<Self, Self::Error> {
+ let system_clock_frequency =
+ *clocking.reference_clock * *clocking.multiplier as f32;
+ clocking.reference_clock * clocking.multiplier as f32;
+ Ok(Profile {
+ frequency_tuning_word: frequency_to_ftw(
+ *channel.dds.frequency,
+ channel.dds.frequency,
+ system_clock_frequency,
+ )?,
+ phase_offset: phase_to_pow(*channel.dds.phase_offset)?,
+ amplitude_control: amplitude_to_acr(*channel.dds.amplitude)?,
+ phase_offset: phase_to_pow(channel.dds.phase_offset)?,
+ amplitude_control: amplitude_to_acr(channel.dds.amplitude)?,
+ })
+ }
}
-#[derive(Serialize, Deserialize, Copy, Clone, Debug)]
-pub struct DdsClockConfig {
- pub multiplier: u8,
- pub reference_clock: f32,
- pub external_clock: bool,
-pub struct OutputChannelState {
+#[derive(Serialize, Deserialize, Copy, Clone, Debug, Tree)]
+pub struct ChannelConfig {
+ #[tree]
+ pub dds: DdsChannelConfig,
+ pub attenuation: Leaf<f32>,
+}
+
pub attenuation: f32,
- pub channel: DdsChannelState,
}
-#[derive(Serialize, Deserialize, Copy, Clone, Debug)]
-pub struct DdsClockConfig {
+impl Default for ChannelConfig {
+ fn default() -> Self {
+ ChannelConfig {
+ dds: DdsChannelConfig::default(),
+ attenuation: 31.5.into(),
+ attenuation: 31.5,
+ }
+ }
+}
+
+#[derive(Serialize, Deserialize, Copy, Clone, Debug, PartialEq, Tree)]
+pub struct ClockConfig {
+ pub multiplier: Leaf<u8>,
+ pub reference_clock: Leaf<f32>,
+ pub external_clock: Leaf<bool>,
+}
+
pub multiplier: u8,
pub reference_clock: f32,
pub external_clock: bool,
}
+impl Default for ClockConfig {
+ fn default() -> Self {
+ Self {
+ multiplier: 5.into(),
+ reference_clock: (MegaHertz::MHz(100).to_Hz() as f32).into(),
+ external_clock: false.into(),
+ multiplier: 5,
+ reference_clock: MegaHertz::MHz(100).to_Hz() as f32,
+ external_clock: false,
+ }
+ }
+}
@ -661,14 +603,16 @@ index 8cf1fb5c..8cc99423 100644
+pub struct PounderConfig {
+ #[tree]
+ pub clock: ClockConfig,
+ #[tree]
+ #[tree(depth = 2)]
+ pub in_channel: [ChannelConfig; 2],
+ #[tree]
+ #[tree(depth = 2)]
+ pub out_channel: [ChannelConfig; 2],
}
+}
+
impl From<Channel> for ad9959::Channel {
@@ -585,3 +647,79 @@ impl rf_power::PowerMeasurementInterface for PounderDevices {
/// Translate pounder channels to DDS output channels.
fn from(other: Channel) -> Self {
@@ -585,3 +651,78 @@ impl rf_power::PowerMeasurementInterface for PounderDevices {
Ok(adc_scale * 2.048)
}
}
@ -681,23 +625,22 @@ index 8cf1fb5c..8cc99423 100644
+ ) {
+ if *clocking != settings.clock {
+ match validate_clocking(
+ *settings.clock.reference_clock,
+ *settings.clock.multiplier,
+ settings.clock.reference_clock,
+ settings.clock.multiplier,
+ ) {
+ Ok(_frequency) => {
+ self.pounder
+ .set_ext_clk(*settings.clock.external_clock)
+ .set_ext_clk(settings.clock.external_clock)
+ .unwrap();
+
+ // skip since ad9959 should already set up the clock
+ // self.dds_output
+ // .builder()
+ // .set_system_clock(
+ // *settings.clock.reference_clock,
+ // *settings.clock.multiplier,
+ // )
+ // .unwrap()
+ // .write();
+ self.dds_output
+ .builder()
+ .set_system_clock(
+ settings.clock.reference_clock,
+ settings.clock.multiplier,
+ )
+ .unwrap()
+ .write();
+
+ *clocking = settings.clock;
+ }
@ -725,7 +668,7 @@ index 8cf1fb5c..8cc99423 100644
+
+ if let Err(err) = self.pounder.set_attenuation(
+ pounder_channel,
+ *channel_config.attenuation,
+ channel_config.attenuation,
+ ) {
+ log::error!("Invalid attenuation settings: {:?}", err)
+ }
@ -748,24 +691,11 @@ index 8cf1fb5c..8cc99423 100644
+ }
+ }
+}
diff --git a/src/net/data_stream.rs b/src/net/data_stream.rs
index 94b2fb6c..510b9e6a 100644
--- a/src/net/data_stream.rs
+++ b/src/net/data_stream.rs
@@ -25,7 +25,7 @@
#![allow(non_camel_case_types)] // https://github.com/rust-embedded/heapless/issues/411
-use core::{fmt::Write, mem::MaybeUninit, net::SocketAddr};
+use core::{fmt::Write, mem::{MaybeUninit, size_of_val}, net::SocketAddr};
use heapless::{
box_pool,
pool::boxed::{Box, BoxBlock},
diff --git a/src/net/mod.rs b/src/net/mod.rs
index 8d815e51..5541f8ba 100644
index a10b7cdb..efa2b8c8 100644
--- a/src/net/mod.rs
+++ b/src/net/mod.rs
@@ -32,14 +32,14 @@ pub type NetworkReference =
@@ -33,14 +33,14 @@ pub type NetworkReference =
pub struct MqttStorage {
telemetry: [u8; 2048],
@ -783,10 +713,10 @@ index 8d815e51..5541f8ba 100644
}
}
diff --git a/src/net/telemetry.rs b/src/net/telemetry.rs
index a368c014..30dfd0c3 100644
index 4aa82601..3dc3086c 100644
--- a/src/net/telemetry.rs
+++ b/src/net/telemetry.rs
@@ -16,7 +16,7 @@ use minimq::Publication;
@@ -16,7 +16,7 @@ use minimq::{DeferredPublication, Publication};
use serde::Serialize;
use super::NetworkReference;
@ -821,8 +751,8 @@ index a368c014..30dfd0c3 100644
+ pub config: PounderConfig,
}
impl TelemetryBuffer {
@@ -77,10 +97,17 @@ impl TelemetryBuffer {
impl Default for TelemetryBuffer {
@@ -87,10 +107,17 @@ impl TelemetryBuffer {
/// * `afe0` - The current AFE configuration for channel 0.
/// * `afe1` - The current AFE configuration for channel 1.
/// * `cpu_temp` - The current CPU temperature.
@ -838,10 +768,10 @@ index a368c014..30dfd0c3 100644
+ cpu_temp: f32,
+ pounder: Option<PounderTelemetry>,
+ ) -> Telemetry {
let in0_volts = f32::from(self.adcs[0]) / afe0.gain();
let in1_volts = f32::from(self.adcs[1]) / afe1.gain();
let in0_volts = Into::<f32>::into(self.adcs[0]) / afe0.as_multiplier();
let in1_volts = Into::<f32>::into(self.adcs[1]) / afe1.as_multiplier();
@@ -89,6 +116,7 @@ impl TelemetryBuffer {
@@ -99,6 +126,7 @@ impl TelemetryBuffer {
adcs: [in0_volts, in1_volts],
dacs: [self.dacs[0].into(), self.dacs[1].into()],
digital_inputs: self.digital_inputs,

28
mcu-contrib/pounder-cargo-patch.diff Normal file
View File

@ -0,0 +1,28 @@
diff --git a/Cargo.lock b/Cargo.lock
index 7c796acf..cee5ba60 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -983,9 +983,9 @@ dependencies = [
[[package]]
name = "serde"
-version = "1.0.203"
+version = "1.0.202"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7253ab4de971e72fb7be983802300c30b5a7f0c2e56fab8abfc6a214307c0094"
+checksum = "226b61a0d411b2ba5ff6d7f73a476ac4f8bb900373459cd00fab8512828ba395"
dependencies = [
"serde_derive",
]
@@ -1003,9 +1003,9 @@ dependencies = [
[[package]]
name = "serde_derive"
-version = "1.0.203"
+version = "1.0.202"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "500cbc0ebeb6f46627f50f3f5811ccf6bf00643be300b4c3eabc0ef55dc5b5ba"
+checksum = "6048858004bcff69094cd972ed40a32500f153bd3be9f716b2eed2e8217c4838"
dependencies = [
"proc-macro2",
"quote",

8
web.nix
View File

@ -8,13 +8,7 @@ in
web-intl = pkgs.runCommand "web-intl" {}
''
cd ${web-src}
export DOMAINNAME=m-labs-intl.com
${pkgs.zola}/bin/zola build -o $out -u https://$DOMAINNAME
'';
web-ph = pkgs.runCommand "web-ph" {}
''
cd ${web-src}
DOMAINNAME=m-labs.hk ${pkgs.zola}/bin/zola build -o $out -u https://m-labs.ph
DOMAINNAME=m-labs-intl.com ${pkgs.zola}/bin/zola build -o $out
'';
sphinxcontrib-platformpicker = pkgs.python3Packages.buildPythonPackage rec {
pname = "sphinxcontrib-platformpicker";