hydra: add urukul-pld build
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@ -154,6 +154,18 @@
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"phaserSrc": { "type": "git", "value": "https://github.com/quartiq/phaser.git", "emailresponsible": false }
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}
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},
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"urukul-pld": {
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"enabled": 1,
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"type": 1,
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"hidden": false,
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"description": "CPLD/FPGA gateware on Urukul",
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"flake": "git+https://git.m-labs.hk/m-labs/urukul-pld.git",
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"checkinterval": 1200,
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"schedulingshares": 1,
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"enableemail": false,
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"emailoverride": "",
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"keepnr": 50
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},
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"sipyco": {
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"enabled": 1,
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