hydra: add urukul-pld build

This commit is contained in:
Sebastien Bourdeauducq 2025-08-21 09:45:49 +08:00
parent be606566a4
commit 08059b64dc

View File

@ -154,6 +154,18 @@
"phaserSrc": { "type": "git", "value": "https://github.com/quartiq/phaser.git", "emailresponsible": false }
}
},
"urukul-pld": {
"enabled": 1,
"type": 1,
"hidden": false,
"description": "CPLD/FPGA gateware on Urukul",
"flake": "git+https://git.m-labs.hk/m-labs/urukul-pld.git",
"checkinterval": 1200,
"schedulingshares": 1,
"enableemail": false,
"emailoverride": "",
"keepnr": 50
},
"sipyco": {
"enabled": 1,