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support now-pinning on RISC-V with wide data bus #97

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opened 2021-11-13 12:02:09 +08:00 by sb10q · 0 comments
sb10q commented 2021-11-13 12:02:09 +08:00
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For FPGA design reasons, on RISC-V with 64-bit data bus (the rv32g target), the now value is split into two 32-bit values that are each padded to 64-bits.

This needs to be ported to NAC3:
0f660735bf

For FPGA design reasons, on RISC-V with 64-bit data bus (the ``rv32g`` target), the ``now`` value is split into two 32-bit values that are each padded to 64-bits. This needs to be ported to NAC3: https://github.com/m-labs/artiq/commit/0f660735bfb85d032277d1a1394d9465cb376250
ychenfo was assigned by sb10q 2021-11-13 12:02:09 +08:00
sb10q closed this issue 2021-11-16 18:29:39 +08:00
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Reference: M-Labs/nac3#97
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