LLVM ERROR: Type mismatch in constant table! #241

New Issue

Closed

opened 2022-03-26 16:15:52 +08:00 by sb10q · 6 comments

sb10q commented 2022-03-26 16:15:52 +08:00

Owner

Copy Link

Patch ARTIQ as follows:

diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index 23d2856f..f8d0e1ff 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -158,7 +158,7 @@ class AD9910:
     ftw_per_hz: KernelInvariant[float]
     sysclk_per_mu: KernelInvariant[int32]
     sysclk: KernelInvariant[float]
-    sw: KernelInvariant[TTLOut]
+    sw: KernelInvariant[Option[TTLOut]]
     sync_data: KernelInvariant[SyncDataUser]
     phase_mode: Kernel[int32]
 
@@ -175,8 +175,9 @@ class AD9910:
         assert 3 <= chip_select <= 7
         self.chip_select = chip_select
         if sw_device:
-            self.sw = dmgr.get(sw_device)
-            # NAC3TODO: support no sw
+            self.sw = Some(dmgr.get(sw_device))
+        else:
+            self.sw = none
         clk = self.cpld.refclk / [4, 1, 2, 4][self.cpld.clk_div]
         self.pll_en = pll_en
         self.pll_n = pll_n
diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py
index bd5daa78..5a4af26b 100644
--- a/artiq/coredevice/ad9912.py
+++ b/artiq/coredevice/ad9912.py
@@ -1,6 +1,6 @@
 from numpy import int32, int64
 
-from artiq.language.core import KernelInvariant, nac3, kernel, portable
+from artiq.language.core import *
 from artiq.language.units import ms, us, ns
 from artiq.coredevice.ad9912_reg import *
 
@@ -35,7 +35,7 @@ class AD9912:
     chip_select: KernelInvariant[int32]
     pll_n: KernelInvariant[int32]
     ftw_per_hz: KernelInvariant[float]
-    sw: KernelInvariant[TTLOut]
+    sw: KernelInvariant[Option[TTLOut]]
 
     def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
                  pll_n=10):
@@ -45,8 +45,9 @@ class AD9912:
         assert 4 <= chip_select <= 7
         self.chip_select = chip_select
         if sw_device:
-            self.sw = dmgr.get(sw_device)
-            # NAC3TODO: support no sw
+            self.sw = Some(dmgr.get(sw_device))
+        else:
+            self.sw = none
         self.pll_n = pll_n
         sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
         assert sysclk <= 1e9
diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py
index ab03201e..d28dff76 100644
--- a/artiq/coredevice/urukul.py
+++ b/artiq/coredevice/urukul.py
@@ -1,11 +1,11 @@
 from numpy import int32, int64
 
-from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable
+from artiq.language.core import *
 from artiq.language.units import us, ms
 
 from artiq.coredevice.core import Core
 from artiq.coredevice.spi2 import *
-from artiq.coredevice.ttl import TTLOut
+from artiq.coredevice.ttl import TTLOut, TTLClockGen
 
 
 SPI_CONFIG = (0 * SPI_OFFLINE | 0 * SPI_END |
@@ -104,15 +104,6 @@ def urukul_sta_proto_rev(sta: int32) -> int32:
     """Return the PROTO_REV value from Urukul status register value."""
     return (sta >> STA_PROTO_REV) & 0x7f
 
-@nac3
-class _DummySync:
-    def __init__(self, cpld):
-        self.cpld = cpld
-
-    @kernel
-    def set_mu(self, ftw: int32):
-        pass
-
 
 @nac3
 class CPLD:
@@ -159,7 +150,8 @@ class CPLD:
     bus: KernelInvariant[SPIMaster]
     io_update: KernelInvariant[TTLOut]
     clk_div: KernelInvariant[int32]
-    sync: KernelInvariant[_DummySync]
+    dds_reset: KernelInvariant[Option[TTLOut]]
+    sync: KernelInvariant[Option[TTLClockGen]]
     cfg_reg: Kernel[int32]
     att_reg: Kernel[int32]
     sync_div: Kernel[int32]
@@ -183,15 +175,15 @@ class CPLD:
             # NAC3TODO
             raise NotImplementedError
         if dds_reset_device is not None:
-            self.dds_reset = dmgr.get(dds_reset_device)
+            self.dds_reset = Some(dmgr.get(dds_reset_device))
+        else:
+            self.dds_reset = none
         if sync_device is not None:
-            self.sync = dmgr.get(sync_device)
+            self.sync = Some(dmgr.get(sync_device))
             if sync_div is None:
                 sync_div = 2
-            # NAC3TODO
-            raise NotImplementedError
         else:
-            self.sync = _DummySync(self)
+            self.sync = none
             assert sync_div is None
             sync_div = 0
 
@@ -420,7 +412,8 @@ class CPLD:
         ftw_max = 1 << 4
         ftw = ftw_max // div
         # NAC3TODO assert ftw * div == ftw_max
-        self.sync.set_mu(ftw)
+        if self.sync.is_some():
+            self.sync.unwrap().set_mu(ftw)
 
     @kernel
     def set_profile(self, profile: int32):
diff --git a/artiq/examples/nac3devices/nac3devices.py b/artiq/examples/nac3devices/nac3devices.py
index c76c4a09..7bc98738 100644
--- a/artiq/examples/nac3devices/nac3devices.py
+++ b/artiq/examples/nac3devices/nac3devices.py
@@ -67,7 +67,7 @@ class NAC3Devices(EnvExperiment):
         self.core.break_realtime()
         self.urukul0_cpld.init()
         self.urukul0_ch0.init()
-        self.urukul0_ch0.sw.on()
+        self.urukul0_ch0.sw.unwrap().on()
         for i in range(10):
             self.urukul0_ch0.set((10. + float(i))*MHz)
             self.urukul0_ch0.set_att(6.)

> artiq_compile nac3devices.py
LLVM ERROR: Type mismatch in constant table!
fish: Job 1, 'artiq_compile nac3devices.py' terminated by signal SIGABRT (Abort)

Patch ARTIQ as follows: ``` diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 23d2856f..f8d0e1ff 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -158,7 +158,7 @@ class AD9910: ftw_per_hz: KernelInvariant[float] sysclk_per_mu: KernelInvariant[int32] sysclk: KernelInvariant[float] - sw: KernelInvariant[TTLOut] + sw: KernelInvariant[Option[TTLOut]] sync_data: KernelInvariant[SyncDataUser] phase_mode: Kernel[int32] @@ -175,8 +175,9 @@ class AD9910: assert 3 <= chip_select <= 7 self.chip_select = chip_select if sw_device: - self.sw = dmgr.get(sw_device) - # NAC3TODO: support no sw + self.sw = Some(dmgr.get(sw_device)) + else: + self.sw = none clk = self.cpld.refclk / [4, 1, 2, 4][self.cpld.clk_div] self.pll_en = pll_en self.pll_n = pll_n diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py index bd5daa78..5a4af26b 100644 --- a/artiq/coredevice/ad9912.py +++ b/artiq/coredevice/ad9912.py @@ -1,6 +1,6 @@ from numpy import int32, int64 -from artiq.language.core import KernelInvariant, nac3, kernel, portable +from artiq.language.core import * from artiq.language.units import ms, us, ns from artiq.coredevice.ad9912_reg import * @@ -35,7 +35,7 @@ class AD9912: chip_select: KernelInvariant[int32] pll_n: KernelInvariant[int32] ftw_per_hz: KernelInvariant[float] - sw: KernelInvariant[TTLOut] + sw: KernelInvariant[Option[TTLOut]] def __init__(self, dmgr, chip_select, cpld_device, sw_device=None, pll_n=10): @@ -45,8 +45,9 @@ class AD9912: assert 4 <= chip_select <= 7 self.chip_select = chip_select if sw_device: - self.sw = dmgr.get(sw_device) - # NAC3TODO: support no sw + self.sw = Some(dmgr.get(sw_device)) + else: + self.sw = none self.pll_n = pll_n sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n assert sysclk <= 1e9 diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index ab03201e..d28dff76 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -1,11 +1,11 @@ from numpy import int32, int64 -from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable +from artiq.language.core import * from artiq.language.units import us, ms from artiq.coredevice.core import Core from artiq.coredevice.spi2 import * -from artiq.coredevice.ttl import TTLOut +from artiq.coredevice.ttl import TTLOut, TTLClockGen SPI_CONFIG = (0 * SPI_OFFLINE | 0 * SPI_END | @@ -104,15 +104,6 @@ def urukul_sta_proto_rev(sta: int32) -> int32: """Return the PROTO_REV value from Urukul status register value.""" return (sta >> STA_PROTO_REV) & 0x7f -@nac3 -class _DummySync: - def __init__(self, cpld): - self.cpld = cpld - - @kernel - def set_mu(self, ftw: int32): - pass - @nac3 class CPLD: @@ -159,7 +150,8 @@ class CPLD: bus: KernelInvariant[SPIMaster] io_update: KernelInvariant[TTLOut] clk_div: KernelInvariant[int32] - sync: KernelInvariant[_DummySync] + dds_reset: KernelInvariant[Option[TTLOut]] + sync: KernelInvariant[Option[TTLClockGen]] cfg_reg: Kernel[int32] att_reg: Kernel[int32] sync_div: Kernel[int32] @@ -183,15 +175,15 @@ class CPLD: # NAC3TODO raise NotImplementedError if dds_reset_device is not None: - self.dds_reset = dmgr.get(dds_reset_device) + self.dds_reset = Some(dmgr.get(dds_reset_device)) + else: + self.dds_reset = none if sync_device is not None: - self.sync = dmgr.get(sync_device) + self.sync = Some(dmgr.get(sync_device)) if sync_div is None: sync_div = 2 - # NAC3TODO - raise NotImplementedError else: - self.sync = _DummySync(self) + self.sync = none assert sync_div is None sync_div = 0 @@ -420,7 +412,8 @@ class CPLD: ftw_max = 1 << 4 ftw = ftw_max // div # NAC3TODO assert ftw * div == ftw_max - self.sync.set_mu(ftw) + if self.sync.is_some(): + self.sync.unwrap().set_mu(ftw) @kernel def set_profile(self, profile: int32): diff --git a/artiq/examples/nac3devices/nac3devices.py b/artiq/examples/nac3devices/nac3devices.py index c76c4a09..7bc98738 100644 --- a/artiq/examples/nac3devices/nac3devices.py +++ b/artiq/examples/nac3devices/nac3devices.py @@ -67,7 +67,7 @@ class NAC3Devices(EnvExperiment): self.core.break_realtime() self.urukul0_cpld.init() self.urukul0_ch0.init() - self.urukul0_ch0.sw.on() + self.urukul0_ch0.sw.unwrap().on() for i in range(10): self.urukul0_ch0.set((10. + float(i))*MHz) self.urukul0_ch0.set_att(6.) ``` ``` > artiq_compile nac3devices.py LLVM ERROR: Type mismatch in constant table! fish: Job 1, 'artiq_compile nac3devices.py' terminated by signal SIGABRT (Abort) ```

sb10q added this to the Prealpha milestone 2022-03-26 16:15:52 +08:00

sb10q added the

high-priority

label 2022-03-26 16:15:52 +08:00

sb10q referenced this issue 2022-03-26 16:57:51 +08:00

LLVM ERROR: Type mismatch in constant table! #225

sb10q commented 2022-03-26 17:24:19 +08:00

Author

Owner

Copy Link

This is caused by the changes in urukul.py. Updated patch:

diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py
index ab03201e..d28dff76 100644
--- a/artiq/coredevice/urukul.py
+++ b/artiq/coredevice/urukul.py
@@ -1,11 +1,11 @@
 from numpy import int32, int64
 
-from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable
+from artiq.language.core import *
 from artiq.language.units import us, ms
 
 from artiq.coredevice.core import Core
 from artiq.coredevice.spi2 import *
-from artiq.coredevice.ttl import TTLOut
+from artiq.coredevice.ttl import TTLOut, TTLClockGen
 
 
 SPI_CONFIG = (0 * SPI_OFFLINE | 0 * SPI_END |
@@ -104,15 +104,6 @@ def urukul_sta_proto_rev(sta: int32) -> int32:
     """Return the PROTO_REV value from Urukul status register value."""
     return (sta >> STA_PROTO_REV) & 0x7f
 
-@nac3
-class _DummySync:
-    def __init__(self, cpld):
-        self.cpld = cpld
-
-    @kernel
-    def set_mu(self, ftw: int32):
-        pass
-
 
 @nac3
 class CPLD:
@@ -159,7 +150,8 @@ class CPLD:
     bus: KernelInvariant[SPIMaster]
     io_update: KernelInvariant[TTLOut]
     clk_div: KernelInvariant[int32]
-    sync: KernelInvariant[_DummySync]
+    dds_reset: KernelInvariant[Option[TTLOut]]
+    sync: KernelInvariant[Option[TTLClockGen]]
     cfg_reg: Kernel[int32]
     att_reg: Kernel[int32]
     sync_div: Kernel[int32]
@@ -183,15 +175,15 @@ class CPLD:
             # NAC3TODO
             raise NotImplementedError
         if dds_reset_device is not None:
-            self.dds_reset = dmgr.get(dds_reset_device)
+            self.dds_reset = Some(dmgr.get(dds_reset_device))
+        else:
+            self.dds_reset = none
         if sync_device is not None:
-            self.sync = dmgr.get(sync_device)
+            self.sync = Some(dmgr.get(sync_device))
             if sync_div is None:
                 sync_div = 2
-            # NAC3TODO
-            raise NotImplementedError
         else:
-            self.sync = _DummySync(self)
+            self.sync = none
             assert sync_div is None
             sync_div = 0
 
@@ -420,7 +412,8 @@ class CPLD:
         ftw_max = 1 << 4
         ftw = ftw_max // div
         # NAC3TODO assert ftw * div == ftw_max
-        self.sync.set_mu(ftw)
+        if self.sync.is_some():
+            self.sync.unwrap().set_mu(ftw)
 
     @kernel
     def set_profile(self, profile: int32):

This is caused by the changes in urukul.py. Updated patch: ``` diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index ab03201e..d28dff76 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -1,11 +1,11 @@ from numpy import int32, int64 -from artiq.language.core import nac3, Kernel, KernelInvariant, kernel, portable +from artiq.language.core import * from artiq.language.units import us, ms from artiq.coredevice.core import Core from artiq.coredevice.spi2 import * -from artiq.coredevice.ttl import TTLOut +from artiq.coredevice.ttl import TTLOut, TTLClockGen SPI_CONFIG = (0 * SPI_OFFLINE | 0 * SPI_END | @@ -104,15 +104,6 @@ def urukul_sta_proto_rev(sta: int32) -> int32: """Return the PROTO_REV value from Urukul status register value.""" return (sta >> STA_PROTO_REV) & 0x7f -@nac3 -class _DummySync: - def __init__(self, cpld): - self.cpld = cpld - - @kernel - def set_mu(self, ftw: int32): - pass - @nac3 class CPLD: @@ -159,7 +150,8 @@ class CPLD: bus: KernelInvariant[SPIMaster] io_update: KernelInvariant[TTLOut] clk_div: KernelInvariant[int32] - sync: KernelInvariant[_DummySync] + dds_reset: KernelInvariant[Option[TTLOut]] + sync: KernelInvariant[Option[TTLClockGen]] cfg_reg: Kernel[int32] att_reg: Kernel[int32] sync_div: Kernel[int32] @@ -183,15 +175,15 @@ class CPLD: # NAC3TODO raise NotImplementedError if dds_reset_device is not None: - self.dds_reset = dmgr.get(dds_reset_device) + self.dds_reset = Some(dmgr.get(dds_reset_device)) + else: + self.dds_reset = none if sync_device is not None: - self.sync = dmgr.get(sync_device) + self.sync = Some(dmgr.get(sync_device)) if sync_div is None: sync_div = 2 - # NAC3TODO - raise NotImplementedError else: - self.sync = _DummySync(self) + self.sync = none assert sync_div is None sync_div = 0 @@ -420,7 +412,8 @@ class CPLD: ftw_max = 1 << 4 ftw = ftw_max // div # NAC3TODO assert ftw * div == ftw_max - self.sync.set_mu(ftw) + if self.sync.is_some(): + self.sync.unwrap().set_mu(ftw) @kernel def set_profile(self, profile: int32): ```

sb10q commented 2022-03-26 17:25:09 +08:00

Author

Owner

Copy Link

And removing dds_reset: KernelInvariant[Option[TTLOut]] makes the error disappear.

And removing ``dds_reset: KernelInvariant[Option[TTLOut]]`` makes the error disappear.

sb10q commented 2022-03-26 17:27:46 +08:00

Author

Owner

Copy Link

And setting dds_reset to a dummy TTLOut (e.g. self.dds_reset = Some(TTLOut(dmgr, 23))) also makes the error disappear. It doesn't like none.

And setting ``dds_reset`` to a dummy ``TTLOut`` (e.g. ``self.dds_reset = Some(TTLOut(dmgr, 23))``) also makes the error disappear. It doesn't like ``none``.

sb10q commented 2022-03-26 17:31:50 +08:00

Author

Owner

Copy Link

Simplified repro:

from artiq.experiment import *
from artiq.coredevice.core import Core
from artiq.coredevice.ttl import TTLOut, TTLClockGen

@nac3
class NAC3Devices(EnvExperiment):
    core: KernelInvariant[Core]
    dds_reset: KernelInvariant[Option[TTLOut]]
    sync: KernelInvariant[Option[TTLClockGen]]

    def build(self):
        self.setattr_device("core")
        self.dds_reset = none
        self.sync = none

    @kernel
    def run(self):
        pass

Using two different empty classes instead of TTLOut / TTLClockGen is not sufficient to reproduce the problem on the other hand.

Simplified repro: ```python from artiq.experiment import * from artiq.coredevice.core import Core from artiq.coredevice.ttl import TTLOut, TTLClockGen @nac3 class NAC3Devices(EnvExperiment): core: KernelInvariant[Core] dds_reset: KernelInvariant[Option[TTLOut]] sync: KernelInvariant[Option[TTLClockGen]] def build(self): self.setattr_device("core") self.dds_reset = none self.sync = none @kernel def run(self): pass ``` Using two different empty classes instead of ``TTLOut`` / ``TTLClockGen`` is not sufficient to reproduce the problem on the other hand.

ychenfo was assigned by sb10q 2022-03-26 17:35:13 +08:00

pca006132 referenced this issue 2022-03-26 18:43:46 +08:00

nac3 segfault with phaser driver #240

ychenfo referenced this issue 2022-03-26 18:49:41 +08:00

nac3 segfault with phaser driver #240

pca006132 referenced this issue 2022-03-26 19:28:51 +08:00

nac3 segfault with phaser driver #240

pca006132 commented 2022-03-26 19:36:56 +08:00

Contributor

Copy Link

Problematic IR:

%artiq_run_nac3devices.NAC3Devices = type { %artiq.coredevice.core.Core*, %artiq.coredevice.ttl.TTLOut**, %artiq.coredevice.ttl.TTLClockGen** }
@"140110844353216" = global %artiq_run_nac3devices.NAC3Devices { %artiq.coredevice.core.Core* @"140110844353168", i8* null, i8* null }

Type mismatch between %artiq.coredevice.ttl.TTLOut** and i8*. I guess you missed a cast? @ychenfo

Problematic IR: ``` %artiq_run_nac3devices.NAC3Devices = type { %artiq.coredevice.core.Core*, %artiq.coredevice.ttl.TTLOut**, %artiq.coredevice.ttl.TTLClockGen** } @"140110844353216" = global %artiq_run_nac3devices.NAC3Devices { %artiq.coredevice.core.Core* @"140110844353168", i8* null, i8* null } ``` Type mismatch between `%artiq.coredevice.ttl.TTLOut**` and `i8*`. I guess you missed a cast? @ychenfo

pca006132 referenced this issue 2022-03-26 19:37:34 +08:00

LLVM ERROR: Type mismatch in constant table! #225

ychenfo commented 2022-03-26 19:39:42 +08:00

Collaborator

Copy Link

Problematic IR:

%artiq_run_nac3devices.NAC3Devices = type { %artiq.coredevice.core.Core*, %artiq.coredevice.ttl.TTLOut**, %artiq.coredevice.ttl.TTLClockGen** }
@"140110844353216" = global %artiq_run_nac3devices.NAC3Devices { %artiq.coredevice.core.Core* @"140110844353168", i8* null, i8* null }

Type mismatch between %artiq.coredevice.ttl.TTLOut** and i8*. I guess you missed a cast? @ychenfo

Yes thanks! I am looking into fix it now.

> Problematic IR: > ``` > %artiq_run_nac3devices.NAC3Devices = type { %artiq.coredevice.core.Core*, %artiq.coredevice.ttl.TTLOut**, %artiq.coredevice.ttl.TTLClockGen** } > @"140110844353216" = global %artiq_run_nac3devices.NAC3Devices { %artiq.coredevice.core.Core* @"140110844353168", i8* null, i8* null } > ``` > > Type mismatch between `%artiq.coredevice.ttl.TTLOut**` and `i8*`. I guess you missed a cast? @ychenfo Yes thanks! I am looking into fix it now.

ychenfo referenced this issue from a commit 2022-03-26 23:34:56 +08:00

nac3artiq: cast none to correct ptr type (#241)

ychenfo referenced this issue 2022-03-27 00:05:37 +08:00

nac3artiq: cast none to correct ptr type (#241) #243

sb10q closed this issue 2022-03-27 08:04:31 +08:00

Sign in to join this conversation.

No Branch/Tag Specified

Branches Tags

master

staging/ndstrides-neo

misc/impl-tracert

ndstrides-14-end

ndstrides-13-tests

ndstrides-12-builtins

ndstrides-11-matmul

ndstrides-10-ops

ndstrides-9-subassign

ndstrides-8-transpose

ndstrides-7-broadcasting

ndstrides-6-reshape

ndstrides-5-miscfuncs

ndstrides-4-nparray

ndstrides-3-indexing

ndstrides-2-basic

ndstrides-1-model

ndstrides-base

misc/update-pyo3

misc/mold

ndstrides-1-model-lifetime

ndstrides-enhance-irrt

ndstrides-intro

issue-313

refactor-primstore

numpy-anyall

enhance/cargo-test-standalone-demos

issue-136

rpc-obj-as-param

iterators

escape-analysis

refactor_anto

No results found.

Labels

Clear labels   

future-extension

  

high-priority

  

low-priority

  

UROP0622

No Label

future-extension

high-priority

low-priority

UROP0622

Milestone

Clear milestone

No items

No Milestone

Prealpha

Assignees

Clear assignees

No Assignees

ychenfo

3 Participants

Notifications

Subscribe

Due Date

The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: M-Labs/nac3#241

No description provided.