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4 Commits

Author SHA1 Message Date
David Mak 50703e515d meta: Allow specifying compiler arguments for check_demos 2023-09-18 11:24:51 +08:00
David Mak 478465e38f artiq: Specify target CPU when creating LLVM target options
We can try to optimize for the host and Cortex-A9 chips; The RISC-V
ISAs do not target specific chips, so we will fallback to using the
generic CPU.
2023-09-18 11:24:51 +08:00
David Mak a324032a9d standalone: Add command line flags for target properties
For testing codegen for different platforms on the host system.
2023-09-18 11:24:51 +08:00
David Mak f0bf40d8b7 core: Switch to LLVM New Pass Manager 2023-09-18 11:24:48 +08:00
3 changed files with 8 additions and 5 deletions

View File

@ -662,7 +662,8 @@ impl Nac3 {
pass_options.set_merge_functions(true);
let result = main.run_passes("default<O3>", &target_machine, pass_options);
if let Err(err) = result {
panic!("Failed to run optimization for module `main`\n{}", err.to_string());
println!("Failed to run optimization for module `main`\n{}", err.to_string());
panic!();
}
link_fn(&main)

View File

@ -334,9 +334,10 @@ impl WorkerRegistry {
let result = module.run_passes(passes.as_str(), &target_machine, pass_options);
if let Err(err) = result {
panic!("Failed to run optimization for module `{}`\n{}",
module.get_name().to_str().unwrap(),
err.to_string());
println!("Failed to run optimization for module `{}`\n{}",
module.get_name().to_str().unwrap(),
err.to_string());
panic!();
}
if self.llvm_options.emit_llvm {

View File

@ -365,7 +365,8 @@ fn main() {
pass_options.set_merge_functions(true);
let result = main.run_passes("default<O3>", &target_machine, pass_options);
if let Err(err) = result {
panic!("Failed to run optimization for module `main`\n{}", err.to_string());
println!("Failed to run optimization for module `main`\n{}", err.to_string());
panic!();
}
target_machine