meta: Allow specifying compiler arguments for check_demos

artiq: Specify target CPU when creating LLVM target options
We can try to optimize for the host and Cortex-A9 chips; The RISC-V ISAs do not target specific chips, so we will fallback to using the generic CPU.
2023-09-15 10:16:47 +08:00 · 2023-09-15 10:16:47 +08:00 · 2023-09-15 10:16:47 +08:00 · 2023-09-15 10:16:47 +08:00
1 changed files with 0 additions and 1 deletions
--- a/nac3artiq/src/lib.rs
+++ b/nac3artiq/src/lib.rs
@ -926,7 +926,6 @@ impl Nac3 {
            deferred_eval_store: DeferredEvaluationStore::new(),
            llvm_options: CodeGenLLVMOptions {
                opt_level: OptimizationLevel::Default,
-                // FIXME(Derppening): Add a field to device_db.py for modifying this option
                legacy_pm: false,
                target: Nac3::get_llvm_target_options(isa),
                emit_llvm: false,
Author	SHA1	Message	Date
David Mak	47c507453c	meta: Allow specifying compiler arguments for check_demos	2023-09-15 10:16:47 +08:00
David Mak	6c2e27c2d9	artiq: Specify target CPU when creating LLVM target options We can try to optimize for the host and Cortex-A9 chips; The RISC-V ISAs do not target specific chips, so we will fallback to using the generic CPU.	2023-09-15 10:16:47 +08:00
David Mak	a033a869cf	standalone: Add command line flags for target properties For testing codegen for different platforms on the host system.	2023-09-15 10:16:47 +08:00
David Mak	3c2696c15c	core: Switch to LLVM New Pass Manager	2023-09-15 10:16:47 +08:00