Merge remote-tracking branch 'origin/master'

* origin/master:
  Fix in_sel comment
  Fix CLK_SEL documentation
  flash_xc3: use standard parameter expansion to default CABLE
  readme: add fxload udev rule and more detailed flashing instructions
  readme: add links to migen and ISE
  flash_xc3: remove fxload call, pass cable type as argument

Makefile

@@ -1,14 +1,15 @@
 .PHONY: all
 all: build
 
-.PHONY: test
-test:
-	python3 mirny_sim.py
+.PHONY: prep
+prep:
+	python3 -m venv --system-site-packages .venv
+	./.venv/bin/pip install -r requirements.txt
 
 .PHONY: build
 build: build/mirny.vm6
 
-build/mirny.vm6: mirny.py mirny_cpld.py
+build/mirny.vm6: mirny.py mirny_cpld.py mirny_impl.py
 	python3 mirny_impl.py
 
 REV:=$(shell git describe --always --abbrev=8 --dirty)

README.md

@@ -8,18 +8,32 @@
 
 ## Building
 
-Needs migen and ISE.
+Needs [migen](https://github.com/m-labs/migen) and [Xilinx ISE](https://www.xilinx.com/products/design-tools/ise-design-suite.html). Assumes ISE is installed in ``/opt/Xilinx``.
 
 ```
 make
-# and then look at/use flash.sh or make flash
-
-# or use fxload and xc3sprog:
-/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum` && sleep 10 && \
-xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
-# look for "Verify: Success"
 ```
 
+## Flashing
+
+With Digilent [JTAG HS2](https://store.digilentinc.com/jtag-hs2-programming-cable/) cable:
+
+  - download firmware to dongle. Manually (adjust USB bus as needed):
+  ```
+  /sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`
+  ```
+  or automatically via the ``udev`` rule:
+  ```
+  SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"
+  ```
+
+  - install [xc3sprog](http://xc3sprog.sourceforge.net/)
+
+  - ``flash_xc3.sh jtaghs2``
+
+  - look for ``Verify: Success``
+
+
 # License
 
 GPLv3+

flash_xc3.sh

@@ -3,6 +3,9 @@
 set -e
 set -x
 
-/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-7.1/devnum`
-sleep 7
-../xc3sprog/build/xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
+XC3SPROG=xc3sprog
+CABLE=${1-xpc}
+
+# /sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-7.1/devnum`
+# sleep 7
+$XC3SPROG -c $CABLE -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w

mirny.py

@@ -223,8 +223,8 @@ class Mirny(Module):
     | Name      | Width | Function                           |
     |-----------+-------+------------------------------------|
     | CE_N      | 4     | PLL chip enable (bar)              |
-    | CLK_SEL   | 2     | Selects CLK source: 0 OSC, 1 MMCX, |
-    |           |       | 2 reserved, 3 SMA                  |
+    | CLK_SEL   | 2     | Selects CLK source:                |
+    |           |       | 0 OSC, 1 reserved, 2 MMCX, 3 SMA   |
     | DIV       | 2     | Clock divider configuration:       |
     |           |       | 0: divide-by-one,                  |
     |           |       | 1: reserved,                       |
@@ -305,7 +305,7 @@ class Mirny(Module):
         clk = platform.request("clk")
         clk_div = TSTriple()
         self.specials += clk_div.get_tristate(clk.div)
-        # in_sel: 00: XO, 01: MMCX, 10: n/a (SMA+XO), 11: SMA
+        # in_sel: 00: XO, 01: n/a (SMA+XO), 10: MMXC, 11: SMA
         # dividers: 00(z): 1, 01(z): 1, 10(low): 2, 11(high) 4
         self.comb += [
             Cat(clk.in_sel, clk_div.o, clk_div.oe).eq(regs[1].write[4:8]),