Robert Jördens e6946d0a36 Merge pull request #7 from Spaqin/almazny_fix
Almazny bug fix: pass MOSI for all channels
2024-08-20 17:22:41 +02:00
2019-06-14 18:37:58 +02:00
2019-06-14 18:37:58 +02:00
2019-06-14 18:37:58 +02:00
2019-06-14 18:37:58 +02:00
2019-06-16 13:16:57 +00:00
2019-06-14 18:37:58 +02:00
2024-06-03 11:31:17 +08:00
2023-02-11 20:57:22 +00:00

Mirny CPLD gateware

Hardware

Hardware

Mirny Schematics

Building

Needs migen and Xilinx ISE. Assumes ISE is installed in /opt/Xilinx.

make

Flashing

With Digilent JTAG HS2 cable:

  • download firmware to dongle. Manually (adjust USB bus as needed):
/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`

or automatically via the udev rule:

SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"
  • install xc3sprog

  • flash_xc3.sh jtaghs2

  • look for Verify: Success

License

GPLv3+

Description
CPLD gateware for the Sinara Mirny module.
Readme 88 KiB
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Python 93.9%
Makefile 2.8%
Shell 2.3%
Batchfile 1%