343 lines
9.3 KiB
Rust
343 lines
9.3 KiB
Rust
use core::ops::{Deref, DerefMut};
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use bit_field::BitField;
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use byteorder::{BigEndian, ByteOrder};
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use super::*;
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pub trait Register {
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type Data: RegisterData;
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fn address(&self) -> u8;
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}
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pub trait RegisterData: Clone + Deref<Target = [u8]> + DerefMut {
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fn empty() -> Self;
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}
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macro_rules! def_reg {
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($Reg:ident, $reg:ident, $addr:expr, $size:expr) => {
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/// AD7172 register
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pub struct $Reg;
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impl Register for $Reg {
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/// Register contents
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type Data = $reg::Data;
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/// Register address
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fn address(&self) -> u8 {
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$addr
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}
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}
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mod $reg {
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/// Register contents
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#[derive(Clone)]
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pub struct Data(pub [u8; $size]);
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impl super::RegisterData for Data {
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/// Generate zeroed register contents
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fn empty() -> Self {
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Data([0; $size])
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}
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}
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impl core::ops::Deref for Data {
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type Target = [u8];
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fn deref(&self) -> &[u8] {
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&self.0
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}
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}
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impl core::ops::DerefMut for Data {
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fn deref_mut(&mut self) -> &mut [u8] {
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&mut self.0
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}
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}
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}
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};
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($Reg:ident,u8, $reg:ident, $addr:expr, $size:expr) => {
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pub struct $Reg {
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pub index: u8,
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}
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impl Register for $Reg {
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type Data = $reg::Data;
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fn address(&self) -> u8 {
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$addr + self.index
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}
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}
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mod $reg {
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#[derive(Clone)]
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pub struct Data(pub [u8; $size]);
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impl super::RegisterData for Data {
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fn empty() -> Self {
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Data([0; $size])
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}
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}
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impl core::ops::Deref for Data {
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type Target = [u8];
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fn deref(&self) -> &[u8] {
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&self.0
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}
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}
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impl core::ops::DerefMut for Data {
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fn deref_mut(&mut self) -> &mut [u8] {
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&mut self.0
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}
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}
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}
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};
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}
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macro_rules! reg_bit {
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($getter:ident, $byte:expr, $bit:expr, $doc:expr) => {
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#[allow(unused)]
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#[doc = $doc]
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pub fn $getter(&self) -> bool {
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self.0[$byte].get_bit($bit)
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}
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};
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($getter:ident, $setter:ident, $byte:expr, $bit:expr, $doc:expr) => {
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#[allow(unused)]
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#[doc = $doc]
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pub fn $getter(&self) -> bool {
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self.0[$byte].get_bit($bit)
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}
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#[allow(unused)]
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#[doc = $doc]
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pub fn $setter(&mut self, value: bool) {
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self.0[$byte].set_bit($bit, value);
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}
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};
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}
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macro_rules! reg_bits {
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($getter:ident, $byte:expr, $bits:expr, $doc:expr) => {
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#[allow(unused)]
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#[doc = $doc]
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pub fn $getter(&self) -> u8 {
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self.0[$byte].get_bits($bits)
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}
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};
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($getter:ident, $setter:ident, $byte:expr, $bits:expr, $doc:expr) => {
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#[allow(unused)]
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#[doc = $doc]
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pub fn $getter(&self) -> u8 {
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self.0[$byte].get_bits($bits)
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}
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#[allow(unused)]
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#[doc = $doc]
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pub fn $setter(&mut self, value: u8) {
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self.0[$byte].set_bits($bits, value);
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}
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};
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($getter:ident, $byte:expr, $bits:expr, $ty:ty, $doc:expr) => {
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#[allow(unused)]
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#[doc = $doc]
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pub fn $getter(&self) -> $ty {
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self.0[$byte].get_bits($bits) as $ty
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}
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};
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($getter:ident, $setter:ident, $byte:expr, $bits:expr, $ty:ty, $doc:expr) => {
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#[allow(unused)]
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#[doc = $doc]
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pub fn $getter(&self) -> $ty {
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self.0[$byte].get_bits($bits).into()
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}
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#[allow(unused)]
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#[doc = $doc]
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pub fn $setter(&mut self, value: $ty) {
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self.0[$byte].set_bits($bits, value as u8);
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}
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};
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}
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def_reg!(Status, status, 0x00, 1);
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impl status::Data {
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/// Is there new data to read?
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pub fn ready(&self) -> bool {
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!self.not_ready()
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}
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reg_bit!(not_ready, 0, 7, "No data ready indicator");
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reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
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reg_bit!(adc_error, 0, 6, "ADC error");
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reg_bit!(crc_error, 0, 5, "SPI CRC error");
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reg_bit!(reg_error, 0, 4, "Register error");
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}
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def_reg!(AdcMode, adc_mode, 0x01, 2);
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impl adc_mode::Data {
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reg_bits!(delay, set_delay, 0, 0..=2, "Delay after channel switch");
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reg_bit!(sing_cyc, set_sing_cyc, 0, 5, "Can only used with single channel");
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reg_bit!(hide_delay, set_hide_delay, 0, 6, "Hide delay");
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reg_bit!(
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ref_en,
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set_ref_en,
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0,
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7,
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"Enable internal reference, output buffered 2.5 V to REFOUT"
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);
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reg_bits!(clockset, set_clocksel, 1, 2..=3, "Clock source");
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reg_bits!(mode, set_mode, 1, 4..=6, Mode, "Operating mode");
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}
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def_reg!(IfMode, if_mode, 0x02, 2);
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impl if_mode::Data {
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reg_bits!(crc, set_crc, 1, 2..=3, ChecksumMode, "SPI checksum mode");
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}
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def_reg!(Data, data, 0x04, 3);
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impl data::Data {
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pub fn data(&self) -> u32 {
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(u32::from(self.0[0]) << 16) | (u32::from(self.0[1]) << 8) | u32::from(self.0[2])
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}
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}
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def_reg!(GpioCon, gpio_con, 0x06, 2);
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impl gpio_con::Data {
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reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
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}
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def_reg!(Id, id, 0x07, 2);
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impl id::Data {
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pub fn id(&self) -> u16 {
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BigEndian::read_u16(&self.0)
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}
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}
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def_reg!(Channel, u8, channel, 0x10, 2);
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impl channel::Data {
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reg_bit!(enabled, set_enabled, 0, 7, "Channel enabled");
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reg_bits!(setup, set_setup, 0, 4..=5, "Setup number");
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/// Which input is connected to positive input of this channel
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#[allow(unused)]
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pub fn a_in_pos(&self) -> Input {
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((self.0[0].get_bits(0..=1) << 3) | self.0[1].get_bits(5..=7)).into()
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}
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/// Set which input is connected to positive input of this channel
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#[allow(unused)]
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pub fn set_a_in_pos(&mut self, value: Input) {
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let value = value as u8;
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self.0[0].set_bits(0..=1, value >> 3);
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self.0[1].set_bits(5..=7, value & 0x7);
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}
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reg_bits!(
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a_in_neg,
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set_a_in_neg,
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1,
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0..=4,
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Input,
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"Which input is connected to negative input of this channel"
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);
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}
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def_reg!(SetupCon, u8, setup_con, 0x20, 2);
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impl setup_con::Data {
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reg_bit!(
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bipolar,
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set_bipolar,
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0,
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4,
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"Unipolar (`false`) or bipolar (`true`) coded output"
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);
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reg_bit!(refbuf_pos, set_refbuf_pos, 0, 3, "Enable REF+ input buffer");
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reg_bit!(refbuf_neg, set_refbuf_neg, 0, 2, "Enable REF- input buffer");
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reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 1, "Enable AIN+ input buffer");
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reg_bit!(ainbuf_neg, set_ainbuf_neg, 0, 0, "Enable AIN- input buffer");
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reg_bit!(
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burnout_en,
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1,
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7,
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"enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the \
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negative analog input selected"
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);
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reg_bits!(
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ref_sel,
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set_ref_sel,
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1,
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4..=5,
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RefSource,
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"Select reference source for conversion"
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);
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}
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def_reg!(FiltCon, u8, filt_con, 0x28, 2);
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impl filt_con::Data {
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reg_bit!(
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sinc3_map,
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set_sinc3_map,
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0,
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7,
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"If set, Sinc3 Filter's notch frequency rejection position can be fine tuned with FiltCon[14:0]. Best to be \
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used with Single Channel Enabled"
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);
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reg_bit!(
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enh_filt_en,
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set_enh_filt_en,
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0,
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3,
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"Enable postfilters for enhanced 50Hz and 60Hz rejection"
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);
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reg_bits!(
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enh_filt,
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set_enh_filt,
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0,
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0..=2,
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PostFilter,
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"Select postfilters output data rate for enhanced 50Hz and 60Hz rejection"
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);
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reg_bits!(
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order,
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set_order,
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1,
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5..=6,
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DigitalFilterOrder,
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"order of the digital filter that processes the modulator data"
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);
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reg_bits!(
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odr,
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set_odr,
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1,
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0..=4,
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SingleChODR,
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"Output data rate for normal Sin5c + Sinc1 and Sinc3 filter with SING_CYC = 0 and Single Channel Enabled"
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);
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reg_bits!(
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sinc3_map_fine_odr_msb,
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set_sinc3_map_fine_odr_msb,
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0,
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0..=6,
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"MSB Byte Sinc3 Fine Output Config"
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);
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reg_bits!(
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sinc3_map_fine_odr_lsb,
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set_sinc3_map_fine_odr_lsb,
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1,
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0..=7,
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"LSB Byte Sinc3 Fine Output Config"
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);
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}
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def_reg!(Offset, u8, offset, 0x30, 3);
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impl offset::Data {
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#[allow(unused)]
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pub fn offset(&self) -> u32 {
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(u32::from(self.0[0]) << 16) | (u32::from(self.0[1]) << 8) | u32::from(self.0[2])
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}
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#[allow(unused)]
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pub fn set_offset(&mut self, value: u32) {
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self.0[0] = (value >> 16) as u8;
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self.0[1] = (value >> 8) as u8;
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self.0[2] = value as u8;
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}
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}
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def_reg!(Gain, u8, gain, 0x38, 3);
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impl gain::Data {
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#[allow(unused)]
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pub fn gain(&self) -> u32 {
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(u32::from(self.0[0]) << 16) | (u32::from(self.0[1]) << 8) | u32::from(self.0[2])
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}
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#[allow(unused)]
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pub fn set_gain(&mut self, value: u32) {
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self.0[0] = (value >> 16) as u8;
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self.0[1] = (value >> 8) as u8;
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self.0[2] = value as u8;
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}
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}
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