laser diode: Add Analog Watchdog initial commit
- rm pid_state for laser diode
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095fe8ea69
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c02181c80c
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@ -0,0 +1,208 @@
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// stm32f4xx_hal does not provide config and driver for analog watchdog yet
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use stm32f4xx_hal::{
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pac::{ADC2, NVIC},
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gpio::{Analog, Output, PushPull, gpioa::PA3, gpiod::PD9},
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interrupt,
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};
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use uom::si::electric_potential::millivolt;
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use uom::si::f64::ElectricPotential;
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// 12 bit Resolution
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const MAX_SAMPLE: u16 = 4095;
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pub type LdPwrEnPinType = PD9<Output<PushPull>>;
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pub type PdMonAdcPinType = PA3<Analog>;
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static mut ANALOG_WDG: Option<LdAnalogWdg> = None;
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pub struct LdAnalogWdgPhy {
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// To make sure PA3 is configured to Analog mode
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pub _pd_mon_ch0: PdMonAdcPinType,
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pub pwr_en_ch0: LdPwrEnPinType,
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}
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#[derive(Clone)]
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pub struct AlarmStatus {
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alarm: bool,
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val: u16,
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}
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pub struct LdAnalogWdg {
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pac: ADC2,
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phy: LdAnalogWdgPhy,
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alarm_status: AlarmStatus,
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//Calibrated VDDA in millivolt from Adc<ADC1>.calibrate()
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calibrated_vdda: u32,
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}
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impl LdAnalogWdg {
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/// ADC interrupt is disabled and continuous conversion is started by default
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pub fn setup(pac: ADC2, phy: LdAnalogWdgPhy){
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unsafe { ANALOG_WDG = Some(LdAnalogWdg{
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pac: pac,
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phy: phy,
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alarm_status: AlarmStatus {
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alarm: false,
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val: 0x0000,
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},
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calibrated_vdda: 3300,
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});
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}
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unsafe {
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.pac.cr1.write(|w| w
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// 12 Bit Resolution
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.res().twelve_bit()
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// Enable Analog Watchdog on Single Regular Channel
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.awden().enabled()
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.awdsgl().single_channel()
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.jawden().disabled()
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// Disable Analog Watchdog Interrupt
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.awdie().disabled()
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// Select Analog Watchdog Channel 3 (PA3) on ADC2
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.awdch().bits(0x03)
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);
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wdg.pac.cr2.write(|w| w
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// Continous Conversion mode
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.cont().set_bit()
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// Enable ADC
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.adon().set_bit()
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// Start ADC Conversion
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.swstart().set_bit()
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);
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// Set Sampling Time for Channel 3 to 480 Cycle
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wdg.pac.smpr2.write(|w| w
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.smp3().cycles480()
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);
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// Set the high threshold to be max value initially
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wdg.pac.htr.write(|w| w.bits(0xFFFF_FFFF));
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// Set the high threshold to be min value initially
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wdg.pac.ltr.write(|w| w.bits(0x0000_0000));
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// Set the Conversion Sequence to only have Channel 3 (PA3)
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wdg.pac.sqr3.write(|w| w
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.sq1().bits(0x03)
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);
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}
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}
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}
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fn get() -> Option<&'static mut Self> {
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unsafe { ANALOG_WDG.as_mut() }
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}
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/// This fn accepts the calibrated vdda value from Adc<ADC1>.calibrate()
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pub fn set_calibrated_vdda(val: u32) {
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.calibrated_vdda = val;
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}
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}
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pub fn get_pd_v() -> ElectricPotential {
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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let sample = wdg.pac.dr.read().data().bits();
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return ElectricPotential::new::<millivolt>(((u32::from(sample) * wdg.calibrated_vdda) / u32::from(MAX_SAMPLE)) as f64)
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}
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ElectricPotential::new::<millivolt>(0.0)
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}
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fn set_alarm(){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.alarm_status = AlarmStatus {
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alarm: true,
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val: wdg.pac.dr.read().data().bits(),
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};
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}
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}
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pub fn get_alarm_status() -> AlarmStatus {
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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return wdg.alarm_status.clone()
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}
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AlarmStatus {
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alarm: false,
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val: 0x0000,
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}
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}
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pub fn clear_alarm_status(){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.alarm_status = AlarmStatus {
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alarm: false,
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val: 0x0000,
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};
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}
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}
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/// Set ADC Watchdog Higher threshold register
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/// Interrupt is triggered when ADC value is ABOVE the value set
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pub fn set_htr(htr: u32){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.pac.htr.write(|w| unsafe {w.bits(htr)});
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}
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}
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/// Set ADC Watchdog Lower threshold register
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/// Interrupt is triggered when ADC value is BELOW the value set
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#[allow(unused)]
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pub fn set_ltr(ltr:u32){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.pac.ltr.write(|w| unsafe {w.bits(ltr)});
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}
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}
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pub fn enable_watchdog_interrupt(){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.pac.cr1.modify(|_, w| w
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.awdie().set_bit()
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);
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}
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}
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pub fn disable_watchdog_interrupt(){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.pac.cr1.modify(|_, w| w
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.awdie().clear_bit()
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);
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}
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}
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fn clear_interrupt_bit(){
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unsafe{
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NVIC::unmask(interrupt::ADC);
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}
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}
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pub fn is_pwr_engaged() -> bool{
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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return wdg.phy.pwr_en_ch0.is_set_high()
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}
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false
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}
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pub fn pwr_engage(){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.phy.pwr_en_ch0.set_high()
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}
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}
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pub fn pwr_disengage(){
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if let Some(ref mut wdg ) = LdAnalogWdg::get() {
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wdg.phy.pwr_en_ch0.set_low()
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}
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}
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}
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#[interrupt]
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fn ADC(){
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cortex_m::interrupt::free(|_| {
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LdAnalogWdg::set_alarm();
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LdAnalogWdg::pwr_disengage();
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// Disable interrupt to avoid getting stuck in infinite interrupt loop
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LdAnalogWdg::disable_watchdog_interrupt();
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LdAnalogWdg::clear_interrupt_bit();
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}
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)
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}
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@ -1,5 +1,5 @@
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pub mod ld_ctrl;
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pub mod max5719;
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pub mod laser_diode;
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pub mod pid_state;
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pub mod pd_mon;
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pub mod pd_mon;
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pub mod analog_wdg;
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