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Fix incorrect Adc filter settings name

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This commit is contained in:
linuswck 2025-01-23 11:51:03 +08:00
parent 7267794e49
commit 6db375d6b8
2 changed files with 8 additions and 8 deletions
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2
pykirdy/driver/kirdy.py
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@ -80,7 +80,7 @@ class CmdList:
class FilterConfig:
class Sinc5Sinc1With50hz60HzRejection(StrEnum):
f27sps = "F27SPS"
f21sps = "F21SPS"
f25sps = "F25SPS"
f20sps = "F20SPS"
f16sps = "F16SPS"
_odr_type = "sinc5sinc1postfilter"

14
src/thermostat/ad7172/mod.rs
View File

@ -148,10 +148,10 @@ impl fmt::Display for RefSource {
#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
#[repr(u8)]
pub enum PostFilter {
/// 27 SPS, 47 dB rejection, 36.7 ms settling
/// 27.27 SPS, 47 dB rejection, 36.7 ms settling
F27SPS = 0b010,
/// 21.25 SPS, 62 dB rejection, 40 ms settling
F21SPS = 0b011,
/// 25 SPS, 62 dB rejection, 40 ms settling
F25SPS = 0b011,
/// 20 SPS, 86 dB rejection, 50 ms settling
F20SPS = 0b101,
/// 16.67 SPS, 92 dB rejection, 60 ms settling
@ -162,7 +162,7 @@ pub enum PostFilter {
impl PostFilter {
pub const VALID_VALUES: &'static [Self] = &[
PostFilter::F27SPS,
PostFilter::F21SPS,
PostFilter::F25SPS,
PostFilter::F20SPS,
PostFilter::F16SPS,
];
@ -182,8 +182,8 @@ impl PostFilter {
/// Samples per Second
pub fn output_rate(&self) -> Option<f32> {
match self {
PostFilter::F27SPS => Some(27.0),
PostFilter::F21SPS => Some(21.25),
PostFilter::F27SPS => Some(27.27),
PostFilter::F25SPS => Some(25.0),
PostFilter::F20SPS => Some(20.0),
PostFilter::F16SPS => Some(16.67),
PostFilter::Invalid => None,
@ -195,7 +195,7 @@ impl From<u8> for PostFilter {
fn from(x: u8) -> Self {
match x {
0b010 => PostFilter::F27SPS,
0b011 => PostFilter::F21SPS,
0b011 => PostFilter::F25SPS,
0b101 => PostFilter::F20SPS,
0b110 => PostFilter::F16SPS,
_ => PostFilter::Invalid,