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Correct SPI Clock Freq and Set them to Max 

- Set the SPI frequency to maximum to reduce data transaction time
- SPI1 SCLK is divided from PCLK2
- SPI2, SPI2 SCLK are divided from PCLK1
master
linuswck 2024-02-26 16:49:00 +08:00
parent 86a9fb039e
commit 19341672a9
3 changed files with 6 additions and 4 deletions
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3
src/laser_diode/max5719.rs
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@ -9,7 +9,8 @@ pub const SPI_MODE: spi::Mode = spi::Mode {
polarity: spi::Polarity::IdleLow,
phase: spi::Phase::CaptureOnFirstTransition,
};
pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(10);
// MAX5719 Max Frequency: 50MHz | SPI2 Max Frequency: 21MHz
pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(21);
pub const MAX_VALUE: u32 = 0xFFFFF;

3
src/thermostat/ad5680.rs
View File

@ -10,7 +10,8 @@ pub const SPI_MODE: spi::Mode = spi::Mode {
polarity: spi::Polarity::IdleLow,
phase: spi::Phase::CaptureOnSecondTransition,
};
pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(30);
// MAX Clock Frequency: 30MHz | SPI1 Max Frequency 42MHz
pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(21);
pub const MAX_VALUE: u32 = 0x3FFFF;

4
src/thermostat/ad7172/mod.rs
View File

@ -15,8 +15,8 @@ pub const SPI_MODE: spi::Mode = spi::Mode {
polarity: spi::Polarity::IdleHigh,
phase: spi::Phase::CaptureOnSecondTransition,
};
/// 2 MHz
pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(2);
/// AD7172 Max Frequency: 40MHz | SPI3 Max Frequency: 21MHz
pub const SPI_CLOCK_MHZ: MegahertzU32 = MegahertzU32::from_raw(21);
pub const MAX_VALUE: u32 = 0xFF_FFFF;