348 lines
12 KiB
Rust
348 lines
12 KiB
Rust
use cortex_m;
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use tm4c129x;
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const LED1: u8 = 0x10; // PK4
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const LED2: u8 = 0x40; // PK6
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const HV_PWM: u8 = 0x01; // PF0
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const FV_PWM: u8 = 0x04; // PF2
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const FBV_PWM: u8 = 0x01; // PD5
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const FD_ADC: u8 = 0x01; // PE0
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const FV_ADC: u8 = 0x02; // PE1
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const FBI_ADC: u8 = 0x04; // PE2
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const IC_ADC: u8 = 0x08; // PE3
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const FBV_ADC: u8 = 0x20; // PD5
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const AV_ADC: u8 = 0x40; // PD6
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const FV_ERRN: u8 = 0x01; // PL0
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const FBV_ERRN: u8 = 0x02; // PL1
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const FBI_ERRN: u8 = 0x04; // PL2
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const AV_ERRN: u8 = 0x08; // PL3
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const AI_ERRN: u8 = 0x10; // PL4
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const ERR_LATCHN: u8 = 0x20; // PL5
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const BTNN: u8 = 0x80; // PL7
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const ERR_RESN: u8 = 0x01; // PQ0
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const PWM_LOAD: u16 = (/*pwmclk*/120_000_000u32 / /*freq*/100_000) as u16;
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const UART_DIV: u32 = (((/*sysclk*/120_000_000 * 8) / /*baud*/115200) + 1) / 2;
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pub const AV_ADC_GAIN: f32 = 6.792703150912105;
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pub const FV_ADC_GAIN: f32 = 501.83449105726623;
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pub const FBI_ADC_GAIN: f32 = 1333.3333333333333;
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pub const FBI_ADC_OFFSET: f32 = 96.0;
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pub const FD_ADC_GAIN: f32 = 3111.1111111111104;
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pub const FD_ADC_OFFSET: f32 = 96.0;
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pub const FBV_ADC_GAIN: f32 = 49.13796058269066;
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pub const FBV_PWM_GAIN: f32 = 0.07641071428571428;
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pub const IC_ADC_GAIN_LOW: f32 = 1333333333333.3333;
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pub const IC_ADC_GAIN_MED: f32 = 13201320132.0132;
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pub const IC_ADC_GAIN_HIGH: f32 = 133320001.3332;
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pub const IC_ADC_OFFSET: f32 = 96.0;
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pub const FBI_R223: f32 = 200.0;
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pub const FBI_R224: f32 = 39.0;
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pub const FBI_R225: f32 = 22000.0;
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pub fn set_led(state: bool) {
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cortex_m::interrupt::free(|_cs| {
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let gpio_k = unsafe { &*tm4c129x::GPIO_PORTK::ptr() };
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if state {
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gpio_k.data.modify(|r, w| w.data().bits(r.data().bits() | LED2))
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} else {
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gpio_k.data.modify(|r, w| w.data().bits(r.data().bits() & !LED2))
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}
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});
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}
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pub fn get_button() -> bool {
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let gpio_dat = cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8
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});
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gpio_dat & BTNN == 0
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}
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pub fn set_hv_pwm(duty: u16) {
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cortex_m::interrupt::free(|_cs| {
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let pwm0 = unsafe { &*tm4c129x::PWM0::ptr() };
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pwm0._0_cmpa.write(|w| w.compa().bits(duty));
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});
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}
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pub fn set_fv_pwm(duty: u16) {
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cortex_m::interrupt::free(|_cs| {
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let pwm0 = unsafe { &*tm4c129x::PWM0::ptr() };
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pwm0._1_cmpa.write(|w| w.compa().bits(duty));
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});
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}
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pub fn set_fbv_pwm(duty: u16) {
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cortex_m::interrupt::free(|_cs| {
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let pwm0 = unsafe { &*tm4c129x::PWM0::ptr() };
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pwm0._2_cmpa.write(|w| w.compa().bits(duty));
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});
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}
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum EmissionRange {
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Low, // 22K
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Med, // 22K//(200Ω + compensated diode)
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High // 22K//(39Ω + uncompensated diode)
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}
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pub fn set_emission_range(range: EmissionRange) {
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cortex_m::interrupt::free(|_cs| {
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let gpio_p = unsafe { &*tm4c129x::GPIO_PORTP::ptr() };
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gpio_p.data.modify(|r, w| {
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let value = r.data().bits() & 0b100111;
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match range {
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EmissionRange::Low => w.data().bits(value | 0b000000),
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EmissionRange::Med => w.data().bits(value | 0b001000),
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EmissionRange::High => w.data().bits(value | 0b010000),
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}
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});
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});
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}
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum ElectrometerRange {
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Low, // 1G
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Med, // 1G//10M
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High // 1G//100K
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}
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pub fn set_electrometer_range(range: ElectrometerRange) {
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cortex_m::interrupt::free(|_cs| {
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let gpio_p = unsafe { &*tm4c129x::GPIO_PORTP::ptr() };
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gpio_p.data.modify(|r, w| {
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let value = r.data().bits() & 0b111100;
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match range {
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ElectrometerRange::Low => w.data().bits(value | 0b000000),
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ElectrometerRange::Med => w.data().bits(value | 0b000001),
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ElectrometerRange::High => w.data().bits(value | 0b000010),
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}
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});
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});
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}
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pub fn reset_error() {
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cortex_m::interrupt::free(|_cs| {
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let gpio_q = unsafe { &*tm4c129x::GPIO_PORTQ::ptr() };
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gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() & !ERR_RESN));
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gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() | ERR_RESN));
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});
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}
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pub fn error_latched() -> bool {
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cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8 & ERR_LATCHN == 0
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})
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}
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pub fn process_errors() {
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let gpio_dat = cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8
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});
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if gpio_dat & FV_ERRN == 0 {
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println!("Filament overvolt");
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}
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if gpio_dat & FBV_ERRN == 0 {
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println!("Filament bias overvolt");
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}
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if gpio_dat & FBI_ERRN == 0 {
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println!("Filament bias overcurrent");
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}
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if gpio_dat & AV_ERRN == 0 {
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println!("Anode overvolt");
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}
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if gpio_dat & AI_ERRN == 0 {
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println!("Anode overcurrent");
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}
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}
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pub fn init() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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// Set up main oscillator
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sysctl.moscctl.write(|w| w.noxtal().bit(false));
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sysctl.moscctl.modify(|_, w| w.pwrdn().bit(false).oscrng().bit(true));
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// Prepare flash for the high-freq clk
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sysctl.memtim0.write(|w| unsafe { w.bits(0x01950195u32) });
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sysctl.rsclkcfg.write(|w| unsafe { w.bits(0x80000000u32) });
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// Set up PLL with fVCO=480 MHz
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sysctl.pllfreq1.write(|w| w.q().bits(0).n().bits(4));
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sysctl.pllfreq0.write(|w| w.mint().bits(96).pllpwr().bit(true));
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sysctl.rsclkcfg.modify(|_, w| w.pllsrc().mosc().newfreq().bit(true));
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while !sysctl.pllstat.read().lock().bit() {}
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// Switch to PLL (sysclk=120MHz)
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sysctl.rsclkcfg.write(|w| unsafe { w.bits(0b1_0_0_1_0011_0000_0000000000_0000000011) });
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// Bring up GPIO ports A, D, E, F, G, K, L, P, Q
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sysctl.rcgcgpio.modify(|_, w| {
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w.r0().bit(true)
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.r3().bit(true)
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.r4().bit(true)
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.r5().bit(true)
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.r6().bit(true)
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.r9().bit(true)
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.r10().bit(true)
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.r13().bit(true)
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.r14().bit(true)
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});
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while !sysctl.prgpio.read().r0().bit() {}
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while !sysctl.prgpio.read().r3().bit() {}
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while !sysctl.prgpio.read().r4().bit() {}
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while !sysctl.prgpio.read().r5().bit() {}
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while !sysctl.prgpio.read().r6().bit() {}
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while !sysctl.prgpio.read().r9().bit() {}
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while !sysctl.prgpio.read().r10().bit() {}
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while !sysctl.prgpio.read().r13().bit() {}
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while !sysctl.prgpio.read().r14().bit() {}
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// Set up UART0
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let gpio_a = unsafe { &*tm4c129x::GPIO_PORTA_AHB::ptr() };
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gpio_a.dir.write(|w| w.dir().bits(0b11));
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gpio_a.den.write(|w| w.den().bits(0b11));
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gpio_a.afsel.write(|w| w.afsel().bits(0b11));
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gpio_a.pctl.write(|w| unsafe { w.pmc0().bits(1).pmc1().bits(1) });
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sysctl.rcgcuart.modify(|_, w| w.r0().bit(true));
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while !sysctl.pruart.read().r0().bit() {}
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let uart_0 = unsafe { &*tm4c129x::UART0::ptr() };
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uart_0.cc.write(|w| w.cs().sysclk());
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uart_0.ibrd.write(|w| w.divint().bits((UART_DIV / 64) as u16));
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uart_0.fbrd.write(|w| w.divfrac().bits((UART_DIV % 64) as u8));
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uart_0.lcrh.write(|w| w.wlen()._8().fen().bit(true));
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uart_0.ctl.write(|w| w.rxe().bit(true).txe().bit(true).uarten().bit(true));
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// Set up LEDs
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let gpio_k = unsafe { &*tm4c129x::GPIO_PORTK::ptr() };
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gpio_k.dir.write(|w| w.dir().bits(LED1|LED2));
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gpio_k.den.write(|w| w.den().bits(LED1|LED2));
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// Switch LED1 to LAN mode
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gpio_k.afsel.modify(|_, w| w.afsel().bits(LED1));
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gpio_k.pctl.modify(|_, w| unsafe { w.pmc4().bits(5) }); // EN0LED0
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// Set up gain and emission range control pins
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let gpio_p = unsafe { &*tm4c129x::GPIO_PORTP::ptr() };
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gpio_p.dir.write(|w| w.dir().bits(0b111111));
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gpio_p.den.write(|w| w.den().bits(0b111111));
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set_emission_range(EmissionRange::Med);
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set_electrometer_range(ElectrometerRange::Med);
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// Set up error and pushbutton pins
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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let gpio_q = unsafe { &*tm4c129x::GPIO_PORTQ::ptr() };
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gpio_l.pur.write(|w| w.pue().bits(FV_ERRN|FBV_ERRN|FBI_ERRN|AV_ERRN|AI_ERRN|BTNN));
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gpio_l.den.write(|w| w.den().bits(FV_ERRN|FBV_ERRN|FBI_ERRN|AV_ERRN|AI_ERRN|ERR_LATCHN|BTNN));
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gpio_q.dir.write(|w| w.dir().bits(ERR_RESN));
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gpio_q.den.write(|w| w.den().bits(ERR_RESN));
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reset_error(); // error latch is an undefined state upon power-up; reset it
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// Set up PWMs
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let gpio_f = unsafe { &*tm4c129x::GPIO_PORTF_AHB::ptr() };
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gpio_f.dir.write(|w| w.dir().bits(HV_PWM|FV_PWM));
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gpio_f.den.write(|w| w.den().bits(HV_PWM|FV_PWM));
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gpio_f.afsel.write(|w| w.afsel().bits(HV_PWM|FV_PWM));
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gpio_f.pctl.write(|w| unsafe { w.pmc0().bits(6).pmc2().bits(6) });
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let gpio_g = unsafe { &*tm4c129x::GPIO_PORTG_AHB::ptr() };
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gpio_g.dir.write(|w| w.dir().bits(FBV_PWM));
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gpio_g.den.write(|w| w.den().bits(FBV_PWM));
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gpio_g.afsel.write(|w| w.afsel().bits(FBV_PWM));
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gpio_g.pctl.write(|w| unsafe { w.pmc0().bits(6) });
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sysctl.rcgcpwm.modify(|_, w| w.r0().bit(true));
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while !sysctl.prpwm.read().r0().bit() {}
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let pwm0 = unsafe { &*tm4c129x::PWM0::ptr() };
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// HV_PWM
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pwm0._0_gena.write(|w| w.actload().zero().actcmpad().one());
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pwm0._0_load.write(|w| w.load().bits(PWM_LOAD));
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pwm0._0_cmpa.write(|w| w.compa().bits(0));
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pwm0._0_ctl.write(|w| w.enable().bit(true));
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// FV_PWM
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pwm0._1_gena.write(|w| w.actload().zero().actcmpad().one());
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pwm0._1_load.write(|w| w.load().bits(PWM_LOAD));
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pwm0._1_cmpa.write(|w| w.compa().bits(0));
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pwm0._1_ctl.write(|w| w.enable().bit(true));
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// FBV_PWM
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pwm0._2_gena.write(|w| w.actload().zero().actcmpad().one());
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pwm0._2_load.write(|w| w.load().bits(PWM_LOAD));
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pwm0._2_cmpa.write(|w| w.compa().bits(0));
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pwm0._2_ctl.write(|w| w.enable().bit(true));
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// Enable all at once
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pwm0.enable.write(|w| {
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w.pwm0en().bit(true)
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.pwm2en().bit(true)
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.pwm4en().bit(true)
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});
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});
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}
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pub fn start_adc() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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let gpio_d = unsafe { &*tm4c129x::GPIO_PORTD_AHB::ptr() };
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let gpio_e = unsafe { &*tm4c129x::GPIO_PORTE_AHB::ptr() };
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gpio_d.afsel.write(|w| w.afsel().bits(FBV_ADC|AV_ADC));
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gpio_d.amsel.write(|w| w.amsel().bits(FBV_ADC|AV_ADC));
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gpio_e.afsel.write(|w| w.afsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
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gpio_e.amsel.write(|w| w.amsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
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sysctl.rcgcadc.modify(|_, w| w.r0().bit(true));
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while !sysctl.pradc.read().r0().bit() {}
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let adc0 = unsafe { &*tm4c129x::ADC0::ptr() };
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// VCO 480 / 15 = 32MHz ADC clock
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adc0.cc.write(|w| w.cs().syspll().clkdiv().bits(15-1));
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adc0.im.write(|w| w.mask0().bit(true));
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adc0.emux.write(|w| w.em0().always());
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adc0.ssmux0.write(|w| {
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w.mux0().bits(0) // IC_ADC
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.mux1().bits(1) // FBI_ADC
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.mux2().bits(2) // FV_ADC
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.mux3().bits(3) // FD_ADC
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.mux4().bits(5) // AV_ADC
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.mux5().bits(6) // FBV_ADC
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});
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adc0.ssctl0.write(|w| w.ie5().bit(true).end5().bit(true));
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adc0.sstsh0.write(|w| {
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w.tsh0()._4()
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.tsh1()._4()
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.tsh2()._4()
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.tsh3()._4()
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.tsh4()._4()
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.tsh5()._4()
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});
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adc0.sac.write(|w| w.avg()._64x());
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adc0.ctl.write(|w| w.vref().bit(true));
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adc0.actss.write(|w| w.asen0().bit(true));
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let mut cp = unsafe { tm4c129x::CorePeripherals::steal() };
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cp.NVIC.enable(tm4c129x::Interrupt::ADC0SS0);
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});
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}
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pub fn get_mac_address() -> [u8; 6] {
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let (userreg0, userreg1) = cortex_m::interrupt::free(|_cs| {
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let flashctl = unsafe { &*tm4c129x::FLASH_CTRL::ptr() };
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(flashctl.userreg0.read().bits(),
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flashctl.userreg1.read().bits())
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});
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[userreg0 as u8, (userreg0 >> 8) as u8, (userreg0 >> 16) as u8,
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userreg1 as u8, (userreg1 >> 8) as u8, (userreg1 >> 16) as u8]
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}
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