board: fix gpio input dir flag

softspi works and ad7172 now returns data.

firmware/src/ad7172.rs

@@ -2,6 +2,7 @@ use embedded_hal::digital::v2::OutputPin;
 use embedded_hal::blocking::spi::Transfer;
 
 #[allow(unused)]
+#[derive(Clone, Copy)]
 #[repr(u8)]
 pub enum Register {
     Status = 0x00,
@@ -33,14 +34,19 @@ pub enum Register {
     Gain3 = 0x3B,
 }
 
+/// AD7172-2 implementation
+///
+/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
 pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
     spi: SPI,
     nss: NSS,
 }
 
 impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
-    pub fn new(spi: SPI, nss: NSS) -> Result<Self, SPI::Error> {
+    pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
+        let _ = nss.set_high();
         let mut adc = Adc { spi, nss};
+        adc.reset()?;
 
         let mut buf = [0, 0, 0];
         adc.write_reg(Register::AdcMode, &mut buf)?;
@@ -52,19 +58,26 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
         Ok(adc)
     }
 
+    /// `0x00DX` for AD7271-2
+    pub fn identify(&mut self) -> Option<u16> {
+        let mut buf = [0u8; 3];
+        self.read_reg(Register::Id, &mut buf)
+            .ok()
+            .map(|()| (u16::from(buf[1]) << 8) | u16::from(buf[2]))
+    }
+
     /// Returns the channel the data is from
     pub fn data_ready(&mut self) -> Option<u8> {
         let mut buf = [0u8; 2];
-        match self.read_reg(Register::Status, &mut buf) {
-            Err(_) => None,
-            Ok(()) => {
+        self.read_reg(Register::Status, &mut buf)
+            .ok()
+            .and_then(|()| {
                 if buf[1] & 0x80 == 0 {
                     None
                 } else {
                     Some(buf[1] & 0x3)
                 }
-            }
-        }
+            })
     }
 
     /// Get data
@@ -78,22 +91,32 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
         Ok(result)
     }
 
+    fn read_reg(&mut self, reg: Register, buffer: &'_ mut [u8]) -> Result<(), SPI::Error> {
+        buffer[0] = 0x40 | (reg as u8);
+        self.transfer(buffer)?;
+        use core::fmt::Write;
+        use cortex_m_semihosting::hio;
+        let mut stdout = hio::hstdout().unwrap();
+        writeln!(stdout, "ad rreg {}: {:?}", reg as u8, buffer);
+        Ok(())
+    }
+
+    fn write_reg(&mut self, reg: Register, buffer: &'_ mut [u8]) -> Result<(), SPI::Error> {
+        buffer[0] = reg as u8;
+        self.transfer(buffer)?;
+        Ok(())
+    }
+
+    pub fn reset(&mut self) -> Result<(), SPI::Error> {
+        let mut buf = [0xFFu8; 8];
+        self.transfer(&mut buf)?;
+        Ok(())
+    }
+
     fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], SPI::Error> {
         let _ = self.nss.set_low();
         let result = self.spi.transfer(words);
         let _ = self.nss.set_high();
         result
     }
-
-    fn read_reg(&mut self, reg: Register, buffer: &'_ mut [u8]) -> Result<(), SPI::Error> {
-        buffer[0] = reg as u8;
-        self.transfer(buffer)?;
-        Ok(())
-    }
-
-    fn write_reg(&mut self, reg: Register, buffer: &'_ mut [u8]) -> Result<(), SPI::Error> {
-        buffer[0] = 0x40 | (reg as u8);
-        self.transfer(buffer)?;
-        Ok(())
-    }
 }

firmware/src/board/gpio.rs

@@ -21,7 +21,7 @@ macro_rules! def_gpio {
             }
             fn into_input(self) -> GpioInput<Self> {
                 let gpio = unsafe { &*tm4c129x::$PORT::ptr() };
-                gpio.dir.modify(|_, w| w.dir().bits(1 << $idx));
+                gpio.dir.modify(|r, w| w.dir().bits(r.dir().bits() & !(1 << $idx)));
                 gpio.den.modify(|_, w| w.den().bits(1 << $idx));
                 GpioInput(self)
             }

firmware/src/board/softspi.rs

@@ -4,7 +4,7 @@ use embedded_hal::blocking::spi::Transfer;
 use embedded_hal::blocking::delay::DelayUs;
 use nb::Error::WouldBlock;
 
-/// Bit-banged SPI
+/// Bit-banged Mode3 SPI
 pub struct SoftSpi<SCK, MOSI, MISO> {
     sck: SCK,
     mosi: MOSI,