ad7172: setup adc
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7e51585aa9
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@ -2,7 +2,10 @@ use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use super::checksum::{ChecksumMode, Checksum};
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use super::AdcError;
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use super::{regs, regs::RegisterData, Input};
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use super::{
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regs, regs::RegisterData,
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Input, RefSource, PostFilter, DigitalFilterOrder,
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};
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/// AD7172-2 implementation
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///
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@ -41,13 +44,27 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
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Ok(())
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}
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pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::GpioCon, |data| {
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data.set_sync_en(enable);
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})
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}
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pub fn setup_channel(
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&mut self, index: u8, in_pos: Input, in_neg: Input
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) -> Result<(), AdcError<SPI::Error>> {
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self.update_reg(®s::SetupCon { index }, |data| {
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data.set_bipolar(false);
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data.set_refbuf_pos(true);
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data.set_refbuf_neg(true);
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data.set_ainbuf_pos(true);
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data.set_ainbuf_neg(true);
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data.set_ref_sel(RefSource::External);
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})?;
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self.update_reg(®s::FiltCon { index }, |data| {
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data.set_enh_filt_en(true);
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data.set_enh_filt(PostFilter::F16SPS);
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data.set_order(DigitalFilterOrder::Sinc5Sinc1);
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// 10 Hz data rate
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data.set_odr(0b10011);
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})?;
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@ -113,9 +113,13 @@ impl fmt::Display for RefSource {
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#[repr(u8)]
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pub enum PostFilter {
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/// 27 SPS, 47 dB rejection, 36.7 ms settling
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F27SPS = 0b010,
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/// 21.25 SPS, 62 dB rejection, 40 ms settling
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F21SPS = 0b011,
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/// 20 SPS, 86 dB rejection, 50 ms settling
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F20SPS = 0b101,
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/// 16.67 SPS, 92 dB rejection, 60 ms settling
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F16SPS = 0b110,
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Invalid = 0b111,
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}
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@ -152,6 +152,11 @@ impl data::Data {
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}
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}
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def_reg!(GpioCon, gpio_con, 0x06, 2);
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impl gpio_con::Data {
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reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
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}
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def_reg!(Id, id, 0x07, 2);
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impl id::Data {
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pub fn id(&self) -> u16 {
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@ -148,6 +148,7 @@ fn main() -> ! {
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writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
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};
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}
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adc.set_sync_enable(false).unwrap();
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// SENS0_{P,N}
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adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
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// SENS1_{P,N}
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