ad7172: add more regs
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8b2cc15d7d
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3ef317f00d
@ -7,6 +7,16 @@ pub enum ChecksumMode {
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Crc = 0b10,
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}
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impl From<u8> for ChecksumMode {
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fn from(x: u8) -> Self {
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match x {
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0 => ChecksumMode::Off,
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1 => ChecksumMode::Xor,
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_ => ChecksumMode::Crc,
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}
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}
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}
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pub struct Checksum {
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mode: ChecksumMode,
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state: u8,
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@ -4,6 +4,18 @@ pub use checksum::ChecksumMode;
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mod adc;
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pub use adc::*;
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#[derive(Clone, Debug, PartialEq)]
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pub enum AdcError<SPI> {
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SPI(SPI),
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ChecksumMismatch(Option<u8>, Option<u8>),
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}
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impl<SPI> From<SPI> for AdcError<SPI> {
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fn from(e: SPI) -> Self {
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AdcError::SPI(e)
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}
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}
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#[repr(u8)]
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pub enum Input {
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Ain0 = 0,
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@ -17,16 +29,85 @@ pub enum Input {
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AnalogSupplyNeg = 20,
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RefPos = 21,
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RefNeg = 22,
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Invalid = 0b11111,
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}
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#[derive(Clone, Debug, PartialEq)]
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pub enum AdcError<SPI> {
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SPI(SPI),
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ChecksumMismatch(Option<u8>, Option<u8>),
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impl From<u8> for Input {
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fn from(x: u8) -> Self {
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match x {
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0 => Input::Ain0,
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1 => Input::Ain1,
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2 => Input::Ain2,
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3 => Input::Ain3,
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4 => Input::Ain4,
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17 => Input::TemperaturePos,
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18 => Input::TemperatureNeg,
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19 => Input::AnalogSupplyPos,
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20 => Input::AnalogSupplyNeg,
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21 => Input::RefPos,
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22 => Input::RefNeg,
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_ => Input::Invalid,
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}
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}
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}
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impl<SPI> From<SPI> for AdcError<SPI> {
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fn from(e: SPI) -> Self {
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AdcError::SPI(e)
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/// Reference source for ADC conversion
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#[repr(u8)]
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pub enum RefSource {
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/// External reference
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External = 0b00,
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/// Internal 2.5V reference
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Internal = 0b10,
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/// AVDD1 − AVSS
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Avdd1MinusAvss = 0b11,
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Invalid = 0b01,
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}
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impl From<u8> for RefSource {
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fn from(x: u8) -> Self {
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match x {
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0 => RefSource::External,
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1 => RefSource::Internal,
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2 => RefSource::Avdd1MinusAvss,
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_ => RefSource::Invalid,
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}
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}
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}
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#[repr(u8)]
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pub enum PostFilter {
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F27SPS = 0b010,
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F21SPS = 0b011,
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F20SPS = 0b101,
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F16SPS = 0b110,
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Invalid = 0b111,
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}
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impl From<u8> for PostFilter {
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fn from(x: u8) -> Self {
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match x {
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0b010 => PostFilter::F27SPS,
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0b011 => PostFilter::F21SPS,
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0b101 => PostFilter::F20SPS,
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0b110 => PostFilter::F16SPS,
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_ => PostFilter::Invalid,
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}
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}
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}
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#[repr(u8)]
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pub enum DigitalFilterOrder {
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Sinc5Sinc1 = 0b00,
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Sinc3 = 0b11,
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Invalid = 0b10,
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}
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impl From<u8> for DigitalFilterOrder {
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fn from(x: u8) -> Self {
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match x {
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0b00 => DigitalFilterOrder::Sinc5Sinc1,
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0b11 => DigitalFilterOrder::Sinc3,
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_ => DigitalFilterOrder::Invalid,
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}
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}
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}
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@ -55,36 +55,77 @@ macro_rules! def_reg {
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}
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}
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macro_rules! reg_bit {
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($getter: ident, $byte: expr, $bit: expr, $doc: expr) => {
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#[doc = $doc]
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pub fn $getter(&self) -> bool {
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self.0[$byte].get_bit($bit)
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}
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};
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($getter: ident, $setter: ident, $byte: expr, $bit: expr, $doc: expr) => {
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#[doc = $doc]
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pub fn $getter(&self) -> bool {
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self.0[$byte].get_bit($bit)
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}
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#[doc = $doc]
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pub fn $setter(&mut self, value: bool) {
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self.0[$byte].set_bit($bit, value);
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}
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};
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}
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macro_rules! reg_bits {
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($getter: ident, $byte: expr, $bits: expr, $doc: expr) => {
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#[doc = $doc]
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pub fn $getter(&self) -> u8 {
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self.0[$byte].get_bits($bits)
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}
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};
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($getter: ident, $setter: ident, $byte: expr, $bits: expr, $doc: expr) => {
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#[doc = $doc]
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pub fn $getter(&self) -> u8 {
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self.0[$byte].get_bits($bits)
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}
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#[doc = $doc]
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pub fn $setter(&mut self, value: u8) {
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self.0[$byte].set_bits($bits, value);
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}
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};
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($getter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
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#[doc = $doc]
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pub fn $getter(&self) -> $ty {
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self.0[$byte].get_bits($bits) as $ty
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}
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};
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($getter: ident, $setter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
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#[doc = $doc]
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pub fn $getter(&self) -> $ty {
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self.0[$byte].get_bits($bits).into()
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}
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#[doc = $doc]
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pub fn $setter(&mut self, value: $ty) {
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self.0[$byte].set_bits($bits, value as u8);
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}
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};
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}
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def_reg!(Status, status, 0x00, 1);
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impl status::Data {
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/// Is there new data to read?
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pub fn ready(&self) -> bool {
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! self.0[0].get_bit(7)
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! self.not_ready()
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}
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/// Channel for which data is ready
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pub fn channel(&self) -> u8 {
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self.0[0].get_bits(0..=1)
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}
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pub fn adc_error(&self) -> bool {
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self.0[0].get_bit(6)
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}
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pub fn crc_error(&self) -> bool {
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self.0[0].get_bit(5)
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}
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pub fn reg_error(&self) -> bool {
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self.0[0].get_bit(4)
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}
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reg_bit!(not_ready, 0, 7, "No data ready indicator");
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reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
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reg_bit!(adc_error, 0, 6, "ADC error");
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reg_bit!(crc_error, 0, 5, "SPI CRC error");
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reg_bit!(reg_error, 0,4, "Register error");
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}
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def_reg!(IfMode, if_mode, 0x02, 2);
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impl if_mode::Data {
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pub fn set_crc(&mut self, mode: ChecksumMode) {
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self.0[1].set_bits(2..=3, mode as u8);
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}
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reg_bits!(crc, set_crc, 1, 2..=3, ChecksumMode, "SPI checksum mode");
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}
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def_reg!(Data, data, 0x04, 3);
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@ -105,48 +146,55 @@ impl id::Data {
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def_reg!(Channel, u8, channel, 0x10, 2);
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impl channel::Data {
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pub fn enabled(&self) -> bool {
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self.0[0].get_bit(7)
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}
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reg_bit!(enabled, set_enabled, 0, 7, "Channel enabled");
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reg_bits!(setup, set_setup, 0, 4..=5, "Setup number");
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pub fn set_enabled(&mut self, value: bool) {
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self.0[0].set_bit(7, value);
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/// Which input is connected to positive input of this channel
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pub fn a_in_pos(&self) -> Input {
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((self.0[0].get_bits(0..=1) << 3) |
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self.0[1].get_bits(5..=7)).into()
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}
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/// Set which input is connected to positive input of this channel
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pub fn set_a_in_pos(&mut self, value: Input) {
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let value = value as u8;
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self.0[0].set_bits(0..=1, value >> 3);
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self.0[1].set_bits(5..=7, value & 0x7);
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}
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reg_bits!(a_in_neg, set_a_in_neg, 1, 0..=4, Input,
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"Which input is connected to negative input of this channel");
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// const PROPS: &'static [Property<Self>] = &[
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// Property::named("enable")
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// .readable(&|self_: &Self| self_.enabled().into())
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// .writebale(&|self_: &mut Self, value| self_.set_enabled(value != 0)),
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// Property::named("setup")
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// .readable(&|self_: &Self| self_.0[0].get_bits(4..=5).into())
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// .writeable(&|self_: &mut Self, value| {
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// self_.0[0].set_bits(4..=5, value as u8);
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// }),
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// ];
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// pub fn props() -> &'static [Property<Self>] {
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// Self::PROPS
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// }
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}
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def_reg!(SetupCon, u8, setup_con, 0x20, 2);
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impl setup_con::Data {
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reg_bit!(bi_unipolar, set_bi_unipolar, 0, 6, "Unipolar (`false`) or bipolar (`true`) coded output");
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reg_bit!(refbuf_pos, set_refbuf_pos, 0, 5, "Enable REF+ input buffer");
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reg_bit!(refbuf_neg, set_refbuf_neg, 0, 5, "Enable REF- input buffer");
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reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 3, "Enable AIN+ input buffer");
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reg_bit!(ainbuf_neg, set_ainbuf_neg, 0, 2, "Enable AIN- input buffer");
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reg_bit!(burnout_en, 1, 7, "enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected");
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reg_bits!(ref_sel, set_ref_sel, 1, 4..=5, RefSource, "Select reference source for conversion");
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}
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def_reg!(FiltCon, u8, filt_con, 0x80, 2);
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// #[allow(unused)]
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// #[derive(Clone, Copy)]
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// #[repr(u8)]
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// pub enum Register {
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// Status = 0x00,
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// AdcMode = 0x01,
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// IfMode = 0x02,
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// RegCheck = 0x03,
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// Data = 0x04,
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// GpioCon = 0x06,
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// Id = 0x07,
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// Ch0 = 0x10,
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// Ch1 = 0x11,
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// Ch2 = 0x12,
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// Ch3 = 0x13,
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// SetupCon0 = 0x20,
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// SetupCon1 = 0x21,
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// SetupCon2 = 0x22,
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// SetupCon3 = 0x23,
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// FiltCon0 = 0x28,
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// FiltCon1 = 0x29,
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// FiltCon2 = 0x2A,
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// FiltCon3 = 0x2B,
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// Offset0 = 0x30,
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// Offset1 = 0x31,
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// Offset2 = 0x32,
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// Offset3 = 0x33,
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// Gain0 = 0x38,
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// Gain1 = 0x39,
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// Gain2 = 0x3A,
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// Gain3 = 0x3B,
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// }
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impl filt_con::Data {
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reg_bit!(sinc3_map, 0, 7, "If set, mapping of filter register changes to directly program the decimation rate of the sinc3 filter");
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reg_bit!(enh_filt_en, set_enh_filt_en, 0, 3, "Enable postfilters for enhanced 50Hz and 60Hz rejection");
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reg_bits!(enh_filt, set_enh_filt, 0, 0..=2, PostFilter, "Select postfilters for enhanced 50Hz and 60Hz rejection");
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reg_bits!(order, set_order, 1, 5..=6, DigitalFilterOrder, "order of the digital filter that processes the modulator data");
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reg_bits!(odr, set_odr, 1, 0..=4, "Output data rate");
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}
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