80 lines
1.8 KiB
Rust
80 lines
1.8 KiB
Rust
#![no_main]
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#![no_std]
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extern crate log;
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use log::debug;
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_rt::entry;
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use firmware::flash::flash_ice40_fpga;
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#[path = "util/logger.rs"]
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mod logger;
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#[entry]
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fn main() -> ! {
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.sys_ck(400.mhz())
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.pll1_q_ck(48.mhz())
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.pll1_r_ck(400.mhz()) // for TRACECK
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.freeze(vos, &dp.SYSCFG);
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unsafe {
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logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
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}
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let delay = cp.SYST.delay(ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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// gpiob.pb3.into_alternate_af0().set_speed(Speed::VeryHigh);
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logger::init();
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debug!("Flashing configuration bitstream to iCE40 HX8K on Humpback.");
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// Using SPI_1 alternate functions (af5)
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let fpga_sck = gpiob.pb3.into_alternate_af5();
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let fpga_sdo = gpiob.pb4.into_alternate_af5();
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let fpga_sdi = gpiob.pb5.into_alternate_af5();
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// Setup SPI_SS_B and CRESET_B
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let fpga_ss = gpioa.pa4.into_push_pull_output();
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let fpga_creset = gpiof.pf3.into_open_drain_output();
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// Setup CDONE
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let fpga_cdone = gpiod.pd15.into_pull_up_input();
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// Setup SPI interface
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let fpga_cfg_spi = dp.SPI1.spi(
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(fpga_sck, fpga_sdo, fpga_sdi),
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spi::MODE_3,
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12.mhz(),
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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// Pre-load the configuration bytes
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let config_data = include_bytes!("../build/top.bin");
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flash_ice40_fpga(fpga_cfg_spi, fpga_ss, fpga_creset, fpga_cdone, delay, config_data).unwrap();
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loop {
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nop();
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}
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}
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