91 lines
1.9 KiB
Rust
91 lines
1.9 KiB
Rust
#![no_main]
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#![no_std]
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use panic_semihosting as _;
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use stm32h7xx_hal::hal::digital::v2::{
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InputPin,
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OutputPin,
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};
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_rt::entry;
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use cortex_m_semihosting::hprintln;
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use core::ptr;
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use nb::block;
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use firmware::CPLD;
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#[entry]
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fn main() -> ! {
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let cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.sys_ck(400.mhz())
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.pll1_q_ck(48.mhz())
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.freeze(vos, &dp.SYSCFG);
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let mut delay = cp.SYST.delay(ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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// Setup CDONE for checking
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let fpga_cdone = gpiod.pd15.into_pull_up_input();
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match fpga_cdone.is_high() {
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Ok(true) => hprintln!("FPGA is ready."),
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Ok(_) => hprintln!("FPGA is in reset state."),
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Err(_) => hprintln!("Error: Cannot read C_DONE"),
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}.unwrap();
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/*
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* Using SPI1, AF5
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* SCLK -> PA5
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* MOSI -> PB5
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* MISO -> PA6
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* CS -> 0: PB12, 1: PA15, 2: PC7
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*/
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let sclk = gpioa.pa5.into_alternate_af5();
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let mosi = gpiob.pb5.into_alternate_af5();
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let miso = gpioa.pa6.into_alternate_af5();
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let mut spi = dp.SPI1.spi(
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(sclk, miso, mosi),
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spi::MODE_0,
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12.mhz(),
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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let mut data :u8 = 0xAD;
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let mut switch = CPLD::new(spi, (
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gpiob.pb12.into_push_pull_output(),
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gpioa.pa15.into_push_pull_output(),
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gpioc.pc7.into_push_pull_output(),
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));
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loop {
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// hprintln!("Sent {}", data).unwrap();
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// block!(spi.send(data)).unwrap();
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// data = block!(spi.read()).unwrap();
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// hprintln!("Read {}", data).unwrap();
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nop();
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}
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}
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