257 lines
5.8 KiB
Rust
257 lines
5.8 KiB
Rust
#![no_main]
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#![no_std]
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use panic_semihosting as _;
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use stm32h7xx_hal::hal::digital::v2::{
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InputPin,
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OutputPin,
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};
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_rt::entry;
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use cortex_m_semihosting::hprintln;
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use core::ptr;
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use nb::block;
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use firmware;
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use firmware::{
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CPLD,
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attenuator::Attenuator,
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config_register::{
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ConfigRegister,
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CFGMask,
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StatusMask,
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},
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dds::DDS,
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};
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#[entry]
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fn main() -> ! {
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let cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.sys_ck(400.mhz())
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.pll1_q_ck(48.mhz())
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.freeze(vos, &dp.SYSCFG);
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let mut delay = cp.SYST.delay(ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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// Setup CDONE for checking
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let fpga_cdone = gpiod.pd15.into_pull_up_input();
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match fpga_cdone.is_high() {
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Ok(true) => hprintln!("FPGA is ready."),
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Ok(_) => hprintln!("FPGA is in reset state."),
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Err(_) => hprintln!("Error: Cannot read C_DONE"),
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}.unwrap();
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/*
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* Using SPI1, AF5
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* SCLK -> PA5
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* MOSI -> PB5
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* MISO -> PA6
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* CS -> 0: PB12, 1: PA15, 2: PC7
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*/
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let sclk = gpioa.pa5.into_alternate_af5();
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let mosi = gpiob.pb5.into_alternate_af5();
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let miso = gpioa.pa6.into_alternate_af5();
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let (cs0, cs1, cs2) = (
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gpiob.pb12.into_push_pull_output(),
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gpioa.pa15.into_push_pull_output(),
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gpioc.pc7.into_push_pull_output(),
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);
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/*
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* I/O_Update -> PB13
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*/
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// TODO: Incoporate io_update into DDS
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let mut io_update = gpiob.pb15.into_push_pull_output();
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let spi = dp.SPI1.spi(
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(sclk, miso, mosi),
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spi::MODE_0,
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3.mhz(),
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let parts = switch.split();
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let mut config = ConfigRegister::new(parts.spi1);
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let mut att = Attenuator::new(parts.spi2);
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let mut dds0 = DDS::new(parts.spi4);
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// Reset all DDS, set CLK_SEL to 0
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config.set_configurations(&mut [
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(CFGMask::RST, 1),
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(CFGMask::IO_RST, 1),
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(CFGMask::IO_UPDATE, 0)
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]).unwrap();
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config.set_configurations(&mut [
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(CFGMask::IO_RST, 0),
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(CFGMask::RST, 0),
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(CFGMask::RF_SW, 1)
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]).unwrap();
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dds0.write_register(0x00, &mut[
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0x00, 0x00, 0x00, 0x02
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]).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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dds0.write_register(0x02, &mut[
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0x01F, 0x3F, 0xC0, 0x00
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]).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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hprintln!("{:#X?}", dds0.read_register(0x00, &mut[
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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// Calculate FTW
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let f_out = 10_000_000;
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let f_sclk = 100_000_000;
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let resolution :u64 = 1 << 32;
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let ftw = (resolution * f_out / f_sclk) as u32;
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hprintln!("{}", ftw);
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// Read single-tone profile 0
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let mut profile :[u8; 8] = [0; 8];
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dds0.read_register(0x0E, &mut profile).unwrap();
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// Overwrite FTW on profile
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profile[4] = ((ftw >> 24) & 0xFF) as u8;
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profile[5] = ((ftw >> 16) & 0xFF) as u8;
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profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
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profile[7] = ((ftw >> 0 ) & 0xFF) as u8;
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dds0.write_register(0x0E, &mut profile).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
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/*
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cs0.set_low().unwrap();
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cs1.set_low().unwrap();
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cs2.set_low().unwrap();
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io_update.set_low().unwrap();
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let mut dummy :[u8;1] = [0];
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spi.transfer(&mut dummy);
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// Master reset DDS_0 through CPLD, with LED at 3
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x08, 0x00, 0x03
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]).unwrap();
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cs0.set_low().unwrap();
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// Perform I/O Reset through CPLD, with LED at 4
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x10, 0x00, 0x04
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]).unwrap();
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cs0.set_low().unwrap();
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// Release reset, control I/O Update through EEM
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// Relay clock signal from internal OSC (CLK_SEL = 0)
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// Enable Switch 0
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x00, 0x00, 0x01
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]).unwrap();
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cs0.set_low().unwrap();
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cs0.set_low().unwrap();
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cs1.set_low().unwrap();
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cs2.set_high().unwrap();
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// Configure SDIO to be input only, enable 3-wires communication
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spi.transfer(&mut [
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0x00, 0x00, 0x00, 0x00, 0x02
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]).unwrap();
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// IO Update after every SPI transfer
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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// Bypass PLL, bypass divisor
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spi.transfer(&mut [
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0x02, 0x1F, 0x3F, 0xC0, 0x00
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]).unwrap();
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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hprintln!("{:#X?}", spi.transfer(&mut [
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0x82, 0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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let f_out = 10_000_000.0;
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let f_sclk = 100_000_000.0;
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let resolution :u64 = 1 << 32;
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let ftw = ((resolution as f32) * f_out / f_sclk) as u32;
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hprintln!("{:#X}", ftw);
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// Read profile 0
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let mut profile_arr_0 :[u8; 9] = [0; 9];
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profile_arr_0[0] = 0x8E;
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hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap();
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// Write FTW to profile 0
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profile_arr_0[0] = 0x0E;
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profile_arr_0[5] = ((ftw >> 24) & 0xFF) as u8;
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profile_arr_0[6] = ((ftw >> 16) & 0xFF) as u8;
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profile_arr_0[7] = ((ftw >> 8 ) & 0xFF) as u8;
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profile_arr_0[8] = ((ftw >> 0 ) & 0xFF) as u8;
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hprintln!("{:#X?}", profile_arr_0).unwrap();
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spi.transfer(&mut profile_arr_0).unwrap();
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// Update after write
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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// Read profile again, new value should be present
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profile_arr_0[0] = 0x8E;
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hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap();
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*/
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loop {}
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}
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