73 lines
1.8 KiB
Rust
73 lines
1.8 KiB
Rust
// Enables ITM
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pub unsafe fn enable_itm(
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dbgmcu: &stm32h7xx_hal::stm32::DBGMCU,
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dcb: &mut cortex_m::peripheral::DCB,
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itm: &mut cortex_m::peripheral::ITM,
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) {
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// ARMv7-M DEMCR: Set TRCENA. Enables DWT and ITM units
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//unsafe { *(0xE000_EDFC as *mut u32) |= 1 << 24 };
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dcb.enable_trace();
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// Ensure debug blocks are clocked before interacting with them
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dbgmcu.cr.modify(|_, w| {
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w.d1dbgcken()
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.set_bit()
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.d3dbgcken()
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.set_bit()
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.traceclken()
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.set_bit()
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.dbgsleep_d1()
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.set_bit()
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});
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// SWO: Unlock
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*(0x5c00_3fb0 as *mut u32) = 0xC5ACCE55;
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// SWTF: Unlock
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*(0x5c00_4fb0 as *mut u32) = 0xC5ACCE55;
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// SWO CODR Register: Set SWO speed
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*(0x5c00_3010 as *mut _) = 200;
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// SWO SPPR Register:
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// 1 = Manchester
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// 2 = NRZ
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*(0x5c00_30f0 as *mut _) = 2;
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// SWTF Trace Funnel: Enable for CM7
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*(0x5c00_4000 as *mut u32) |= 1;
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// ITM: Unlock
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itm.lar.write(0xC5ACCE55);
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// ITM Trace Enable Register: Enable lower 8 stimulus ports
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itm.ter[0].write(1);
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// ITM Trace Control Register: Enable ITM
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itm.tcr.write(
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(0b000001 << 16) | // TraceBusID
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(1 << 3) | // enable SWO output
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(1 << 0), // enable the ITM
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);
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}
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use panic_itm as _;
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use lazy_static::lazy_static;
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use log::LevelFilter;
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pub use cortex_m_log::log::Logger;
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use cortex_m_log::{
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destination::Itm as ItmDest, modes::InterruptFree, printer::itm::InterruptSync,
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printer::itm::ItmSync,
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};
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lazy_static! {
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static ref LOGGER: Logger<ItmSync<InterruptFree>> = Logger {
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level: LevelFilter::Info,
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inner: unsafe { InterruptSync::new(ItmDest::new(cortex_m::Peripherals::steal().ITM)) },
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};
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}
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pub fn init() {
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cortex_m_log::log::init(&LOGGER).unwrap();
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}
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