105 lines
3.2 KiB
Python
105 lines
3.2 KiB
Python
import argparse
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# Import built in I/O, Connectors & Platform template for Humpback
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from migen.build.platforms.sinara import humpback
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# Import migen pin record structure
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from migen.build.generic_platform import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.genlib.io import *
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class UrukulConnector(Module):
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def __init__(self, platform, eem_resource_name):
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# Include extension
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spi_mosi = [
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("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
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]
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spi_cs = [
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("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
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]
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io_update = [
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("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
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]
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# Add extensions
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platform.add_extension(spi_cs)
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platform.add_extension(io_update)
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platform.add_extension(spi_mosi)
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# Request EEM I/O & SPI
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eem = [
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platform.request(eem_resource_name, 0),
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platform.request(eem_resource_name, 1),
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# Supply EEM pin with negative polarity
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# See issue/PR: https://github.com/m-labs/migen/pull/181
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platform.request(f"{eem_resource_name}_n", 2),
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platform.request(eem_resource_name, 3),
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platform.request(eem_resource_name, 4),
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platform.request(eem_resource_name, 5),
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platform.request(eem_resource_name, 6)
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]
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spi = platform.request("spi")
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spi_mosi = platform.request("spi_mosi")
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spi_cs = platform.request("spi_cs")
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led = platform.request("user_led")
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io_update = platform.request("io_update")
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assert len(spi.clk) == 1
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assert len(spi_mosi) == 1
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assert len(spi.miso) == 1
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assert len(spi_cs) == 3
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assert len(io_update) == 1
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# Flip negative input to positive output
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self.miso_n = Signal()
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# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
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self.specials += Instance("SB_IO",
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p_PIN_TYPE=C(0b000001, 6),
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p_IO_STANDARD="SB_LVDS_INPUT",
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io_PACKAGE_PIN=eem[2],
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o_D_IN_0=self.miso_n
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)
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# Link EEM to SPI
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self.comb += [
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eem[0].p.eq(spi.clk),
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eem[0].n.eq(~spi.clk),
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eem[1].p.eq(spi_mosi),
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eem[1].n.eq(~spi_mosi),
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spi.miso.eq(~self.miso_n),
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eem[3].p.eq(spi_cs[0]),
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eem[3].n.eq(~spi_cs[0]),
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eem[4].p.eq(spi_cs[1]),
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eem[4].n.eq(~spi_cs[1]),
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eem[5].p.eq(spi_cs[2]),
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eem[5].n.eq(~spi_cs[2]),
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eem[6].p.eq(io_update),
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eem[6].n.eq(~io_update),
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led.eq(1)
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]
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if __name__ == "__main__":
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parser = argparse.ArgumentParser(description="Build FPGA bitstream")
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parser.add_argument(
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"--eem",
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type=int,
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choices=[0, 1, 2],
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default=0,
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help="The Humpback EEM port the Urukul board is connected to."
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)
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args = parser.parse_args()
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platform = humpback.Platform()
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platform.build(UrukulConnector(platform, f"eem{args.eem}"))
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