#![no_main]
#![no_std]

use panic_semihosting as _;

use stm32h7xx_hal::hal::digital::v2::{
	InputPin,
	OutputPin,
};
use stm32h7xx_hal::{pac, prelude::*, spi};

use cortex_m;
use cortex_m::asm::nop;
use cortex_m_rt::entry;
use cortex_m_semihosting::hprintln;

use core::ptr;
use nb::block;

use firmware;
use firmware::{
	CPLD,
	attenuator::Attenuator,
	config_register::{
		ConfigRegister,
		CFGMask,
		StatusMask,
	},
	dds::DDS,
};

#[entry]
fn main() -> ! {

	let cp = cortex_m::Peripherals::take().unwrap();
	let dp = pac::Peripherals::take().unwrap();

	let pwr = dp.PWR.constrain();
	let vos = pwr.freeze();

	let rcc = dp.RCC.constrain();
	let ccdr = rcc
		.sys_ck(400.mhz())
		.pll1_q_ck(48.mhz())
		.freeze(vos, &dp.SYSCFG);
	
	let mut delay = cp.SYST.delay(ccdr.clocks);

	let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
	let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
	let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
	let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
	let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
	let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);

	// Setup CDONE for checking
	let fpga_cdone = gpiod.pd15.into_pull_up_input();

	match fpga_cdone.is_high() {
		Ok(true)	=> hprintln!("FPGA is ready."),
		Ok(_)		=> hprintln!("FPGA is in reset state."),
		Err(_)		=> hprintln!("Error: Cannot read C_DONE"),
	}.unwrap();

	/*
	 *	Using SPI1, AF5
	 *  SCLK -> PA5
	 *	MOSI -> PB5
	 *	MISO -> PA6
	 *	CS -> 0: PB12, 1: PA15, 2: PC7
	 */

	let sclk = gpioa.pa5.into_alternate_af5();
	let mosi = gpiob.pb5.into_alternate_af5();
	let miso = gpioa.pa6.into_alternate_af5();


	let (cs0, cs1, cs2) = (
		gpiob.pb12.into_push_pull_output(),
		gpioa.pa15.into_push_pull_output(),
		gpioc.pc7.into_push_pull_output(),
	);

	/*
	 *	I/O_Update -> PB13
	 */
	let io_update = gpiob.pb15.into_push_pull_output();

	let spi = dp.SPI1.spi(
		(sclk, miso, mosi),
		spi::MODE_0,
		3.mhz(),
		ccdr.peripheral.SPI1,
		&ccdr.clocks,
	);

	let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
	let parts = switch.split();

	let mut config = ConfigRegister::new(parts.spi1);
	let mut att = Attenuator::new(parts.spi2);
	let mut dds0 = DDS::new(parts.spi4);

	// Reset all DDS, set CLK_SEL to 0
	config.set_configurations(&mut [
		(CFGMask::RST, 1),
		(CFGMask::IO_RST, 1),
		(CFGMask::IO_UPDATE, 0)
	]).unwrap();

	config.set_configurations(&mut [
		(CFGMask::IO_RST, 0),
		(CFGMask::RST, 0),
		(CFGMask::RF_SW, 1)
	]).unwrap();

	dds0.write_register(0x00, &mut[
		0x00, 0x00, 0x00, 0x02
	]).unwrap();

	dds0.write_register(0x02, &mut[
		0x01F, 0x3F, 0x41, 0x00
	]).unwrap();

	hprintln!("{:#X?}", dds0.read_register(0x00, &mut[
		0x00, 0x00, 0x00, 0x00
	]).unwrap()).unwrap();

	// Calculate FTW
	let f_out = 10_000_000;
	let f_sclk = 100_000_000;
	let resolution :u64 = 1 << 32;
	let ftw = (resolution * f_out / f_sclk) as u32;
	
	hprintln!("{}", ftw);

	// Read single-tone profile 0
	let mut profile :[u8; 8] = [0; 8];
	dds0.read_register(0x0E, &mut profile).unwrap();

	// Overwrite FTW on profile
	profile[0] = 0x20;
	profile[4] = ((ftw >> 24) & 0xFF) as u8;
	profile[5] = ((ftw >> 16) & 0xFF) as u8;
	profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
	profile[7] = ((ftw >> 0 ) & 0xFF) as u8;

	dds0.write_register(0x0E, &mut profile).unwrap();

	hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();

	// Attenuator
	att.set_attenuation([
		0.0, 31.5, 24.0, 0.0
	]).unwrap();

	hprintln!("{:#X?}", att.get_attenuation().unwrap()).unwrap();

/*
	// Write to FTW register
	dds0.write_register(0x07, &mut [
		((ftw >> 24) & 0xFF) as u8,
		((ftw >> 16) & 0xFF) as u8,
		((ftw >> 8 ) & 0xFF) as u8,
		((ftw >> 0 ) & 0xFF) as u8,
	]).unwrap();

	hprintln!("{:#X?}", dds0.read_register(0x07, &mut [
		0x00, 0x00, 0x00, 0x00
	]).unwrap()).unwrap();
*/	
	loop {}
}