from humpback import HumpbackPlatform from migen.fhdl.module import Module from migen.fhdl.specials import Instance from migen.fhdl.bitcontainer import value_bits_sign from migen.genlib.io import * from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl from migen.genlib.io import DifferentialInput class UrukulConnector(Module): def __init__(self, platform): # Request EEM I/O & SPI eem0 = [ platform.request("eem0", 0), platform.request("eem0", 1), platform.request("eem0_n", 2), platform.request("eem0", 3), platform.request("eem0", 4), platform.request("eem0", 5) ] spi = platform.request("spi") led = platform.request("user_led") # Assert SPI resource length assert len(spi.sclk) == 1 assert len(spi.mosi) == 1 assert len(spi.miso) == 1 assert len(spi.cs) == 3 # TODO: Assert EEM resources assert isinstance(eem0, list) # Flip positive signal as negative output, maybe only do it for FPGA outputs self.miso_n = Signal() # Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead self.specials += Instance("SB_IO", p_PIN_TYPE=C(0b000001, 6), p_IO_STANDARD="SB_LVDS_INPUT", io_PACKAGE_PIN=eem0[2], o_D_IN_0=self.miso_n ) # Link EEM to SPI self.comb += [ eem0[0].p.eq(spi.sclk), eem0[0].n.eq(~spi.sclk), eem0[1].p.eq(spi.mosi), eem0[1].n.eq(~spi.mosi), spi.miso.eq(~self.miso_n), eem0[3].p.eq(spi.cs[0]), eem0[3].n.eq(~spi.cs[0]), eem0[4].p.eq(spi.cs[1]), eem0[4].n.eq(~spi.cs[1]), eem0[5].p.eq(spi.cs[2]), eem0[5].n.eq(~spi.cs[2]), led.eq(1) ] if __name__ == "__main__": platform = HumpbackPlatform() platform.build(UrukulConnector(platform))