#![no_main]
#![no_std]

use panic_semihosting as _;

use stm32h7xx_hal::hal::digital::v2::{
	InputPin,
	OutputPin,
};
use stm32h7xx_hal::{pac, prelude::*, spi};

use cortex_m;
use cortex_m::asm::nop;
use cortex_m_rt::entry;
use cortex_m_semihosting::hprintln;

use core::ptr;
use nb::block;

use firmware;
use firmware::{
	CPLD,
	attenuator::Attenuator,
	config_register::{
		ConfigRegister,
		CFGMask,
	},
	dds::DDS,
};

#[entry]
fn main() -> ! {

	let cp = cortex_m::Peripherals::take().unwrap();
	let dp = pac::Peripherals::take().unwrap();

	let pwr = dp.PWR.constrain();
	let vos = pwr.freeze();

	let rcc = dp.RCC.constrain();
	let ccdr = rcc
		.sys_ck(400.mhz())
		.pll1_q_ck(48.mhz())
		.freeze(vos, &dp.SYSCFG);
	
	let mut delay = cp.SYST.delay(ccdr.clocks);

	let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
	let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
	let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
	let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
	let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);

	// Setup CDONE for checking
	let fpga_cdone = gpiod.pd15.into_pull_up_input();

	match fpga_cdone.is_high() {
		Ok(true)	=> hprintln!("FPGA is ready."),
		Ok(_)		=> hprintln!("FPGA is in reset state."),
		Err(_)		=> hprintln!("Error: Cannot read C_DONE"),
	}.unwrap();

	/*
	 *	Using SPI1, AF5
	 *  SCLK -> PA5
	 *	MOSI -> PB5
	 *	MISO -> PA6
	 *	CS -> 0: PB12, 1: PA15, 2: PC7
	 */

	let sclk = gpioa.pa5.into_alternate_af5();
	let mosi = gpiob.pb5.into_alternate_af5();
	let miso = gpioa.pa6.into_alternate_af5();

	let (cs0, cs1, cs2) = (
		gpiob.pb12.into_push_pull_output(),
		gpioa.pa15.into_push_pull_output(),
		gpioc.pc7.into_push_pull_output(),
	);

	let mut spi = dp.SPI1.spi(
		(sclk, miso, mosi),
		spi::MODE_0,
		12.mhz(),
		ccdr.peripheral.SPI1,
		&ccdr.clocks,
	);

	let mut switch = CPLD::new(spi, (cs0, cs1, cs2));

	let parts = switch.split();

	let mut attenuator = Attenuator::new(parts.spi2);
	let mut attenuation :[f32; 4] = [24.0, -5.0, 32.0, 10.2];
	attenuator.set_attenuation(attenuation);
	attenuator.set_channel_attenuation(2, 15.3);

	let mut config = ConfigRegister::new(parts.spi1);
	// Target configuration: 0x000FF1CE
	hprintln!("{:#06X}", config.set_configurations(&mut [
		(CFGMask::RF_SW,		0xE),
		(CFGMask::LED,			0xC),
		(CFGMask::PROFILE,		0x1),
		(CFGMask::IO_UPDATE,	0x1),
		(CFGMask::MASK_NU,		0xF),
		(CFGMask::CLK_SEL0,		0x1),
		(CFGMask::SYNC_SEL,		0x1),
		(CFGMask::RST,			0x1),
		(CFGMask::IO_RST,		0x0),
		(CFGMask::CLK_SEL1,		0x0),
		(CFGMask::DIV,			0x0),
	]).unwrap()).unwrap();

	let mut dds = DDS::new(parts.spi4);

	loop {
		nop();
	}
}