Merge branch 'master' of https://git.m-labs.hk/occheung/firmware-development

Cargo.lock

@@ -456,7 +456,6 @@ source = "git+https://github.com/smoltcp-rs/smoltcp.git#bdfa44270e9c59b3095b555c
 dependencies = [
  "bitflags",
  "byteorder",
- "log",
  "managed",
 ]
 

Cargo.toml

@@ -11,9 +11,8 @@ cortex-m = "0.6.2"
 cortex-m-rt = "0.6.12"
 embedded-hal = "0.2.4"
 stm32h7xx-hal = {version = "0.7.1", features = [ "stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a" ] }
-smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp", "log" ] }
+smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp" ] }
 nb = "1.0.0"
-
 embedded-nal = "0.1.0"
 minimq = { git = "https://github.com/quartiq/minimq.git", branch = "master" }
 heapless = "0.5.6"

Makefile

@@ -1,5 +0,0 @@
-fpga_config: main.rs
-	openocd -f openocd/openocd.cfg -f openocd/main.cfg
-
-main.rs: top.bin
-	cargo build --release

build.rs

@@ -2,9 +2,9 @@ use std::process::Command;
 
 fn main() {
     Command::new("python3")
-    		.arg("migen/fpga_config.py")
+    		.arg("fpga/fpga_config.py")
     		.spawn()
     		.expect("FPGA bitstream file cannot be built!");
 
-    println!("cargo:rerun-if-changed=migen/fpga_config.py")
+    println!("cargo:rerun-if-changed=fpga/fpga_config.py")
 }

fpga/fpga_config.py

@@ -0,0 +1,92 @@
+# Import built in I/O, Connectors & Platform template for Humpback
+from migen.build.platforms.sinara import humpback
+# Import migen pin record structure
+from migen.build.generic_platform import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.genlib.io import *
+
+
+class UrukulConnector(Module):
+    def __init__(self, platform):
+        # Include extension
+        spi_mosi = [
+            ("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
+        ]
+        spi_cs = [
+            ("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
+        ]
+        io_update = [
+            ("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
+        ]
+
+        # Add extensions
+        platform.add_extension(spi_cs)
+        platform.add_extension(io_update)
+        platform.add_extension(spi_mosi)
+
+        # Request EEM I/O & SPI
+        eem0 = [
+            platform.request("eem0", 0),
+            platform.request("eem0", 1),
+            # Supply EEM pin with negative polarity
+            # See issue/PR: https://github.com/m-labs/migen/pull/181
+            platform.request("eem0_n", 2),
+            platform.request("eem0", 3),
+            platform.request("eem0", 4),
+            platform.request("eem0", 5),
+            platform.request("eem0", 6)
+        ]
+        spi = platform.request("spi")
+        spi_mosi = platform.request("spi_mosi")
+        spi_cs = platform.request("spi_cs")
+        led = platform.request("user_led")
+        io_update = platform.request("io_update")
+
+        assert len(spi.clk) == 1
+        assert len(spi_mosi) == 1
+        assert len(spi.miso) == 1
+        assert len(spi_cs) == 3
+        assert len(io_update) == 1
+
+        # Flip negative input to positive output
+        self.miso_n = Signal()
+
+        # Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
+        self.specials += Instance("SB_IO",
+                            p_PIN_TYPE=C(0b000001, 6),
+                            p_IO_STANDARD="SB_LVDS_INPUT",
+                            io_PACKAGE_PIN=eem0[2],
+                            o_D_IN_0=self.miso_n
+                        )
+
+        # Link EEM to SPI
+        self.comb += [
+
+            eem0[0].p.eq(spi.clk),
+            eem0[0].n.eq(~spi.clk),
+
+            eem0[1].p.eq(spi_mosi),
+            eem0[1].n.eq(~spi_mosi),
+
+            spi.miso.eq(~self.miso_n),
+
+            eem0[3].p.eq(spi_cs[0]),
+            eem0[3].n.eq(~spi_cs[0]),
+
+            eem0[4].p.eq(spi_cs[1]),
+            eem0[4].n.eq(~spi_cs[1]),
+
+            eem0[5].p.eq(spi_cs[2]),
+            eem0[5].n.eq(~spi_cs[2]),
+
+            eem0[6].p.eq(io_update),
+            eem0[6].n.eq(~io_update),
+
+            led.eq(1)
+        ]
+
+
+if __name__ == "__main__":
+    platform = humpback.Platform()
+    platform.build(UrukulConnector(platform))

migen/fpga_config.py

@@ -1,92 +0,0 @@
-# Import built in I/O, Connectors & Platform template for Humpback
-from migen.build.platforms.sinara import humpback
-# Import migen pin record structure
-from migen.build.generic_platform import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
-from migen.genlib.io import *
-
-
-class UrukulConnector(Module):
-	def __init__(self, platform):
-		# Include extension
-		spi_mosi = [
-			("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
-		]
-		spi_cs = [
-			("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
-		]
-		io_update = [
-			("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
-		]
-
-		# Add extensions
-		platform.add_extension(spi_cs)
-		platform.add_extension(io_update)
-		platform.add_extension(spi_mosi)
-
-		# Request EEM I/O & SPI
-		eem0 = [
-			platform.request("eem0", 0),
-			platform.request("eem0", 1),
-			# Supply EEM pin with negative polarity
-			# See issue/PR: https://github.com/m-labs/migen/pull/181
-			platform.request("eem0_n", 2),
-			platform.request("eem0", 3),
-			platform.request("eem0", 4),
-			platform.request("eem0", 5),
-			platform.request("eem0", 6)
-		]
-		spi = platform.request("spi")
-		spi_mosi = platform.request("spi_mosi")
-		spi_cs = platform.request("spi_cs")
-		led = platform.request("user_led")
-		io_update = platform.request("io_update")
-
-		assert len(spi.clk) == 1
-		assert len(spi_mosi) == 1
-		assert len(spi.miso) == 1
-		assert len(spi_cs) == 3
-		assert len(io_update) == 1
-
-		# Flip negative input to positive output
-		self.miso_n = Signal()
-
-		# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
-		self.specials += Instance("SB_IO",
-							p_PIN_TYPE=C(0b000001, 6),
-							p_IO_STANDARD="SB_LVDS_INPUT",
-							io_PACKAGE_PIN=eem0[2],
-							o_D_IN_0=self.miso_n
-						)
-
-		# Link EEM to SPI
-		self.comb += [
-
-			eem0[0].p.eq(spi.clk),
-			eem0[0].n.eq(~spi.clk),
-
-			eem0[1].p.eq(spi_mosi),
-			eem0[1].n.eq(~spi_mosi),
-
-			spi.miso.eq(~self.miso_n),
-
-			eem0[3].p.eq(spi_cs[0]),
-			eem0[3].n.eq(~spi_cs[0]),
-
-			eem0[4].p.eq(spi_cs[1]),
-			eem0[4].n.eq(~spi_cs[1]),
-
-			eem0[5].p.eq(spi_cs[2]),
-			eem0[5].n.eq(~spi_cs[2]),
-
-			eem0[6].p.eq(io_update),
-			eem0[6].n.eq(~io_update),
-
-			led.eq(1)
-		]
-
-
-if __name__ == "__main__":
-	platform = humpback.Platform()
-	platform.build(UrukulConnector(platform))

src/attenuator.rs

@@ -4,123 +4,123 @@ use core::assert;
 use crate::urukul::Error;
 
 pub struct Attenuator<SPI> {
-	spi: SPI,
+    spi: SPI,
-	data: [u8; 4],
+    data: [u8; 4],
 }
 
 impl<SPI, E> Attenuator<SPI>
 where
-	SPI: Transfer<u8, Error = E>
+    SPI: Transfer<u8, Error = E>
 {
-	pub fn new(spi: SPI) -> Self {
+    pub fn new(spi: SPI) -> Self {
-		Attenuator {
+        Attenuator {
-			spi,
+            spi,
-			// data[y] refers to the yth byte for SPI communication
+            // data[y] refers to the yth byte for SPI communication
-			data: [0, 0, 0, 0],
+            data: [0, 0, 0, 0],
-		}
+        }
-	}
+    }
 
-	/*
+    /*
-	 *  Set attenuations of all attenuators
+     *  Set attenuations of all attenuators
-	 *  att[x] refers to the attenuation for channel x
+     *  att[x] refers to the attenuation for channel x
-	 */
+     */
-	pub fn set_attenuation(&mut self, att: [f32; 4]) -> Result<(), Error<E>> {
+    pub fn set_attenuation(&mut self, att: [f32; 4]) -> Result<(), Error<E>> {
-		for i in 0..4 {
+        for i in 0..4 {
-			let mut atten = att[i];
+            let mut atten = att[i];
-			if att[i] > 31.5 {
+            if att[i] > 31.5 {
-				atten = 31.5;
+                atten = 31.5;
-			}
+            }
-			if att[i] < 0.0 {
+            if att[i] < 0.0 {
-				atten = 0.0;
+                atten = 0.0;
-			}
+            }
-			// Set data as attenuation * 2
+            // Set data as attenuation * 2
-			// Flip data using bitwise XOR, active low data
+            // Flip data using bitwise XOR, active low data
-			// Data is most signifant attenuator first
+            // Data is most signifant attenuator first
-			self.data[3-i] = (((atten * 2.0) as u8) ^ 0xFF) << 2
+            self.data[3-i] = (((atten * 2.0) as u8) ^ 0xFF) << 2
-		}
+        }
-		let mut clone = self.data.clone();
+        let mut clone = self.data.clone();
-		// Transmit SPI once to set attenuation
+        // Transmit SPI once to set attenuation
-		self.spi.transfer(&mut clone)
+        self.spi.transfer(&mut clone)
-						.map(|_| ())
+                        .map(|_| ())
-						.map_err(|_| Error::AttenuatorError)
+                        .map_err(|_| Error::AttenuatorError)
-	}
+    }
 
-	pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
+    pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
-		assert!(channel < 4);
+        assert!(channel < 4);
-		let mut arr: [f32; 4] = self.get_attenuation()?;
+        let mut arr: [f32; 4] = self.get_attenuation()?;
-		arr[channel as usize] = attenuation;
+        arr[channel as usize] = attenuation;
-		self.set_attenuation(arr).map(|_| ())
+        self.set_attenuation(arr).map(|_| ())
-	}
+    }
 
-	pub fn get_channel_attenuation(&mut self, channel: u8) -> Result<f32, Error<E>> {
+    pub fn get_channel_attenuation(&mut self, channel: u8) -> Result<f32, Error<E>> {
-		assert!(channel < 4);
+        assert!(channel < 4);
-		match self.get_attenuation() {
+        match self.get_attenuation() {
-			Ok(arr) => Ok(arr[channel as usize]),
+            Ok(arr) => Ok(arr[channel as usize]),
-			Err(e) => Err(e),
+            Err(e) => Err(e),
-		}
+        }
-	}
+    }
 
-	pub fn get_attenuation(&mut self) -> Result<[f32; 4], Error<E>> {
+    pub fn get_attenuation(&mut self) -> Result<[f32; 4], Error<E>> {
-		let mut clone = self.data.clone();
+        let mut clone = self.data.clone();
-		match self.spi.transfer(&mut clone).map_err(Error::SPI) {
+        match self.spi.transfer(&mut clone).map_err(Error::SPI) {
-			Ok(arr) => {
+            Ok(arr) => {
-				let mut ret :[f32; 4] = [0.0; 4];
+                let mut ret :[f32; 4] = [0.0; 4];
-				for index in 0..4 {
+                for index in 0..4 {
-					ret[index] = ((arr[3 - index] ^ 0xFC) as f32) / 8.0;
+                    ret[index] = ((arr[3 - index] ^ 0xFC) as f32) / 8.0;
-				}
+                }
-				Ok(ret)
+                Ok(ret)
-			},
+            },
-			Err(e) => Err(e),
+            Err(e) => Err(e),
-		}
+        }
-	}
+    }
 
-	/*
+    /*
-	 *  Test method for Attenuators.
+     *  Test method for Attenuators.
-	 *  Return the number of test failed.
+     *  Return the number of test failed.
-	 */
+     */
-	pub fn test(&mut self) -> Result<u32, Error<E>> {
+    pub fn test(&mut self) -> Result<u32, Error<E>> {
-		// Test attenuators by getting back the attenuation
+        // Test attenuators by getting back the attenuation
-		let mut error_count = 0;
+        let mut error_count = 0;
-		// Convert cached SPI data into attenuation floats
+        // Convert cached SPI data into attenuation floats
-		let att_floats :[f32; 4] = [
+        let att_floats :[f32; 4] = [
-			((self.data[3] ^ 0xFC) as f32) / 8.0,
+            ((self.data[3] ^ 0xFC) as f32) / 8.0,
-			((self.data[2] ^ 0xFC) as f32) / 8.0,
+            ((self.data[2] ^ 0xFC) as f32) / 8.0,
-			((self.data[1] ^ 0xFC) as f32) / 8.0,
+            ((self.data[1] ^ 0xFC) as f32) / 8.0,
-			((self.data[0] ^ 0xFC) as f32) / 8.0,
+            ((self.data[0] ^ 0xFC) as f32) / 8.0,
-		];
+        ];
-		// Set the attenuation to an arbitrary value, then read the attenuation
+        // Set the attenuation to an arbitrary value, then read the attenuation
-		self.set_attenuation([
+        self.set_attenuation([
-			3.5, 9.5, 20.0, 28.5
+            3.5, 9.5, 20.0, 28.5
-		])?;
+        ])?;
-		match self.get_attenuation() {
+        match self.get_attenuation() {
-			Ok(arr) => {
+            Ok(arr) => {
-				if arr[0] != 3.5 {
+                if arr[0] != 3.5 {
-					error_count += 1;
+                    error_count += 1;
-				}
+                }
-				if arr[1] != 9.5 {
+                if arr[1] != 9.5 {
-					error_count += 1;
+                    error_count += 1;
-				}
+                }
-				if arr[2] != 20.0 {
+                if arr[2] != 20.0 {
-					error_count += 1;
+                    error_count += 1;
-				}
+                }
-				if arr[3] != 28.5 {
+                if arr[3] != 28.5 {
-					error_count += 1;
+                    error_count += 1;
-				}
+                }
-			},
+            },
-			Err(_) => return Err(Error::AttenuatorError),
+            Err(_) => return Err(Error::AttenuatorError),
-		};
+        };
-		self.set_attenuation(att_floats)?;
+        self.set_attenuation(att_floats)?;
-		Ok(error_count)
+        Ok(error_count)
-	}
+    }
 }
 
 impl<SPI, E> Transfer<u8> for Attenuator<SPI>
 where
-	SPI: Transfer<u8, Error = E>
+    SPI: Transfer<u8, Error = E>
 {
-	type Error = Error<E>;
+    type Error = Error<E>;
 
-	fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
-		self.spi.transfer(words).map_err(Error::SPI)
+        self.spi.transfer(words).map_err(Error::SPI)
-	}
+    }
 }

src/bitmask_macro.rs

@@ -7,51 +7,51 @@
  */
 
 macro_rules! construct_bitmask {
-	($collection: ident; $unsigned_type: ty; $($name: ident, $shift: expr, $width: expr),+) => {
+    ($collection: ident; $unsigned_type: ty; $($name: ident, $shift: expr, $width: expr),+) => {
-		#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+        #[derive(Debug, Copy, Clone, PartialEq, Eq)]
-		#[allow(non_camel_case_types)]
+        #[allow(non_camel_case_types)]
-		pub enum $collection {
+        pub enum $collection {
-			$(
+            $(
-				$name,
+                $name,
-			)*
+            )*
-		}
+        }
 
-		impl $collection {
+        impl $collection {
-			pub(crate) fn get_width(self) -> u8 {
+            pub(crate) fn get_width(self) -> u8 {
-				match self {
+                match self {
-					$(
+                    $(
-						$collection::$name => $width,
+                        $collection::$name => $width,
-					)*
+                    )*
-				}
+                }
-			}
+            }
-			pub(crate) fn get_shift(self) -> u8 {
+            pub(crate) fn get_shift(self) -> u8 {
-				match self {
+                match self {
-					$(
+                    $(
-						$collection::$name => $shift,
+                        $collection::$name => $shift,
-					)*
+                    )*
-				}
+                }
-			}
+            }
-			pub(crate) fn get_bitmask(self) -> $unsigned_type {
+            pub(crate) fn get_bitmask(self) -> $unsigned_type {
-				let mut mask: $unsigned_type = 0;
+                let mut mask: $unsigned_type = 0;
-				for bit in 0..self.get_width() {
+                for bit in 0..self.get_width() {
-					mask |= (1 << (self.get_shift() + bit) % ((size_of::<$unsigned_type>() as u8) * 8));
+                    mask |= (1 << (self.get_shift() + bit) % ((size_of::<$unsigned_type>() as u8) * 8));
-				}
+                }
-				mask
+                mask
-			}
+            }
-			pub(crate) fn get_shifted_bits(self, arg: $unsigned_type) -> $unsigned_type {
+            pub(crate) fn get_shifted_bits(self, arg: $unsigned_type) -> $unsigned_type {
-				assert!(arg < (2 << self.get_width()));
+                assert!(arg < (2 << self.get_width()));
-				(arg << (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
+                (arg << (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
-			}
+            }
-			#[allow(dead_code)]
+            #[allow(dead_code)]
-			pub(crate) fn set_data_by_arg(self, data: &mut $unsigned_type, arg: $unsigned_type) {
+            pub(crate) fn set_data_by_arg(self, data: &mut $unsigned_type, arg: $unsigned_type) {
-				// Clear bits in field, then insert shifted argument
+                // Clear bits in field, then insert shifted argument
-				*data &= (!self.get_bitmask());
+                *data &= (!self.get_bitmask());
-				*data |= self.get_shifted_bits(arg);
+                *data |= self.get_shifted_bits(arg);
-			}
+            }
-			pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type {
+            pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type {
-				// Filter everything then shift bits
+                // Filter everything then shift bits
-				((data & self.get_bitmask()) >> (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
+                ((data & self.get_bitmask()) >> (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
-			}
+            }
-		}
+        }
-	}
+    }
 }

src/config_register.rs

@@ -4,121 +4,121 @@ use core::mem::size_of;
 
 // Bitmasks for CFG
 construct_bitmask!(CFGMask; u32;
-	RF_SW,		0,	4,
+    RF_SW,        0,     4,
-	LED,		4,	4,
+    LED,          4,     4,
-	PROFILE,	8,	3,
+    PROFILE,      8,     3,
-	IO_UPDATE,	12,	1,
+    IO_UPDATE,    12,    1,
-	MASK_NU,	13,	4,
+    MASK_NU,      13,    4,
-	CLK_SEL0,	17,	1,
+    CLK_SEL0,     17,    1,
-	SYNC_SEL,	18,	1,
+    SYNC_SEL,     18,    1,
-	RST,		19,	1,
+    RST,          19,    1,
-	IO_RST,		20,	1,
+    IO_RST,       20,    1,
-	CLK_SEL1,	21,	1,
+    CLK_SEL1,     21,    1,
-	DIV,		22,	2
+    DIV,          22,    2
 );
 
 // BitMasks for CFG read
 construct_bitmask!(StatusMask; u32;
-	RF_SW,		0,	4,
+    RF_SW,        0,     4,
-	SMP_ERR,	4,	4,
+    SMP_ERR,      4,     4,
-	PLL_LOCK,	8,	4,
+    PLL_LOCK,     8,     4,
-	IFC_MODE,	12,	4,
+    IFC_MODE,     12,    4,
-	PROTO_KEY,	16,	7	
+    PROTO_KEY,    16,    7    
 );
 
 pub struct ConfigRegister<SPI> {
-	spi: SPI,
+    spi: SPI,
-	data: u32,
+    data: u32,
 }
 
 impl<SPI, E> ConfigRegister<SPI>
 where
-	SPI: Transfer<u8, Error = E>
+    SPI: Transfer<u8, Error = E>
 {
-	pub fn new(spi: SPI) -> Self {
+    pub fn new(spi: SPI) -> Self {
-		ConfigRegister {
+        ConfigRegister {
-			spi,
+            spi,
-			data: 0,
+            data: 0,
-		}
+        }
-	}
+    }
 
-	/*
+    /*
-	 * Set configuration bits according to data field
+     * Set configuration bits according to data field
-	 * Return status
+     * Return status
-	 */
+     */
-	fn set_all_configurations(&mut self) -> Result<u32, Error<E>> {
+    fn set_all_configurations(&mut self) -> Result<u32, Error<E>> {
-		match self.spi.transfer(&mut [
+        match self.spi.transfer(&mut [
-			((self.data & 0x00FF0000) >> 16) as u8,
+            ((self.data & 0x00FF0000) >> 16) as u8,
-			((self.data & 0x0000FF00) >>  8) as u8,
+            ((self.data & 0x0000FF00) >>  8) as u8,
-			((self.data & 0x000000FF) >>  0) as u8,
+            ((self.data & 0x000000FF) >>  0) as u8,
-		]).map_err(Error::SPI) {
+        ]).map_err(Error::SPI) {
-			Ok(arr) => Ok(
+            Ok(arr) => Ok(
-				((arr[0] as u32) << 16) |
+                ((arr[0] as u32) << 16) |
-				((arr[1] as u32) <<  8) |
+                ((arr[1] as u32) <<  8) |
-				arr[2] as u32
+                arr[2] as u32
-			),
+            ),
-			Err(e) => Err(e),
+            Err(e) => Err(e),
-		}
+        }
-	}
+    }
 
-	/*
+    /*
-	 * Set configuration bits according to supplied configs
+     * Set configuration bits according to supplied configs
-	 * Return status
+     * Return status
-	 */	
+     */    
-	pub fn set_configurations(&mut self, configs: &mut[(CFGMask, u32)]) -> Result<u32, Error<E>> {
+    pub fn set_configurations(&mut self, configs: &mut[(CFGMask, u32)]) -> Result<u32, Error<E>> {
-		for config in configs.into_iter() {
+        for config in configs.into_iter() {
-			config.0.set_data_by_arg(&mut self.data, config.1)
+            config.0.set_data_by_arg(&mut self.data, config.1)
-		}
+        }
-		// Write all configurations at the same time
+        // Write all configurations at the same time
-		self.set_all_configurations()
+        self.set_all_configurations()
-	}
+    }
 
-	/*
+    /*
-	 * Return selected configuration field
+     * Return selected configuration field
-	 */
+     */
-	pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
+    pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
-		config_type.get_filtered_content(self.data) as u8
+        config_type.get_filtered_content(self.data) as u8
-	}
+    }
 
-	/*
+    /*
-	 * Return status using mask
+     * Return status using mask
-	 */
+     */
-	pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
+    pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
-		match self.set_all_configurations() {
+        match self.set_all_configurations() {
-			Ok(val) => Ok(status_type.get_filtered_content(val) as u8),
+            Ok(val) => Ok(status_type.get_filtered_content(val) as u8),
-			Err(e) => Err(e),
+            Err(e) => Err(e),
-		}
+        }
-	}
+    }
 
-	/*
+    /*
-	 * Return entire status register
+     * Return entire status register
-	 */
+     */
-	pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
+    pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
-		return self.set_all_configurations();
+        return self.set_all_configurations();
-	}
+    }
 
-	/*
+    /*
-	 *  Test method for Configuration Register.
+     *  Test method for Configuration Register.
-	 *  Return the number of test failed.
+     *  Return the number of test failed.
-	 */
+     */
-	pub fn test(&mut self) -> Result<u32, Error<E>> {
+    pub fn test(&mut self) -> Result<u32, Error<E>> {
-		// Test configuration register by getting PROTO_KEY.
+        // Test configuration register by getting PROTO_KEY.
-		match self.get_status(StatusMask::PROTO_KEY) {
+        match self.get_status(StatusMask::PROTO_KEY) {
-			Ok(8) => Ok(0),
+            Ok(8) => Ok(0),
-			Ok(_) => Ok(1),
+            Ok(_) => Ok(1),
-			Err(_) => Err(Error::ConfigRegisterError),
+            Err(_) => Err(Error::ConfigRegisterError),
-		}
+        }
-	}
+    }
 }
 
 impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>
 where
-	SPI: Transfer<u8, Error = E>
+    SPI: Transfer<u8, Error = E>
 {
-	type Error = Error<E>;
+    type Error = Error<E>;
 
-	fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
-		self.spi.transfer(words).map_err(Error::SPI)
+        self.spi.transfer(words).map_err(Error::SPI)
-	}
+    }
 }
 

src/cpld.rs

@@ -2,14 +2,14 @@ use crate::urukul::Error;
 use crate::spi_slave::Parts;
 
 use embedded_hal::{
-	digital::v2::OutputPin,
+    digital::v2::OutputPin,
-	blocking::spi::Transfer,
+    blocking::spi::Transfer,
 };
 
 use core::cell;
 
 /*
- *	Basic structure for CPLD signal multiplexing
+ *  Basic structure for CPLD signal multiplexing
  */
 #[derive(Debug)]
 pub struct CPLDData<SPI, CS0, CS1, CS2, GPIO> {

src/flash.rs

@@ -1,5 +1,5 @@
 use embedded_hal::{
-	digital::v2::{OutputPin, InputPin},
+    digital::v2::{OutputPin, InputPin},
     blocking::spi::Transfer,
     blocking::delay::DelayUs,
 };
@@ -21,65 +21,65 @@ pub fn flash_ice40_fpga<SPI: Transfer<u8>,
                         DONE: InputPin>
     (mut spi: SPI, mut ss: SS, mut creset: RST, cdone: DONE, mut delay: DELAY) -> Result<(), FPGAFlashError>
 {
-	// Data buffer setup
+    // Data buffer setup
-	let mut dummy_byte :[u8; 1] = [0x00];
+    let mut dummy_byte :[u8; 1] = [0x00];
-	let mut dummy_13_bytes :[u8; 13] = [0x00; 13];
+    let mut dummy_13_bytes :[u8; 13] = [0x00; 13];
 
-	// Drive CRESET_B low
+    // Drive CRESET_B low
     creset.set_low()
             .map_err(|_| FPGAFlashError::NegotiationError)?;
 
-	// Drive SPI_SS_B low
+    // Drive SPI_SS_B low
     ss.set_low()
         .map_err(|_| FPGAFlashError::NegotiationError)?;
 
-	// Wait at least 200ns
+    // Wait at least 200ns
-	delay.delay_us(1_u32);
+    delay.delay_us(1_u32);
 
-	// Drive CRESET_B high
+    // Drive CRESET_B high
     creset.set_high()
             .map_err(|_| FPGAFlashError::NegotiationError)?;
 
-	// Wait at least another 1200us to clear internal config memory
+    // Wait at least another 1200us to clear internal config memory
-	delay.delay_us(1200_u32);
+    delay.delay_us(1200_u32);
 
     // Before data transmission starts, check if C_DONE is truly low
     // If C_DONE is high, the FPGA reset procedure is unsuccessful
-	match cdone.is_low() {
+    match cdone.is_low() {
         Ok(true) => {},
         _ => return Err(FPGAFlashError::ResetStatusError),
     };
 
-	// Set SPI_SS_B high
+    // Set SPI_SS_B high
     ss.set_high()
         .map_err(|_| FPGAFlashError::NegotiationError)?;
 
-	// Send 8 dummy clock, effectively 1 byte of 0x00
+    // Send 8 dummy clock, effectively 1 byte of 0x00
     spi.transfer(&mut dummy_byte)
         .map_err(|_| FPGAFlashError::SPICommunicationError)?;
 
-	// Drive SPI_SS_B low
+    // Drive SPI_SS_B low
     ss.set_low()
         .map_err(|_| FPGAFlashError::NegotiationError)?;
 
-	// Send the whole image without interruption
+    // Send the whole image without interruption
-	for byte in DATA.into_iter() {
+    for byte in DATA.into_iter() {
         let mut single_byte_slice = [*byte];
         spi.transfer(&mut single_byte_slice)
             .map_err(|_| FPGAFlashError::SPICommunicationError)?;
-	}
+    }
 
-	// Drive SPI_SS_B high
+    // Drive SPI_SS_B high
     ss.set_high()
         .map_err(|_| FPGAFlashError::NegotiationError)?;
 
-	// Send at another 100 dummy clocks (choosing 13 bytes)
+    // Send at another 100 dummy clocks (choosing 13 bytes)
     spi.transfer(&mut dummy_13_bytes)
         .map_err(|_| FPGAFlashError::SPICommunicationError)?;
 
     // Check the CDONE output from FPGA
     // CDONE needs to be high
-	match cdone.is_high() {
+    match cdone.is_high() {
         Ok(true) => {},
         _ => return Err(FPGAFlashError::ResetStatusError),
     };

src/main.rs

@@ -1,15 +1,15 @@
 #![no_main]
 #![no_std]
-#![feature(str_strip)]
+#![feature(core_intrinsics)]
-use log::{ trace, debug, info, warn };
+
-use stm32h7xx_hal::hal::digital::v2::InputPin;
+use log::{ trace };
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::{pac, prelude::*, spi};
 use stm32h7xx_hal::ethernet;
 
 use smoltcp as net;
 use minimq::{
-    embedded_nal::{IpAddr, Ipv4Addr, TcpStack},
+    embedded_nal::{ IpAddr, Ipv4Addr },
     MqttClient, QoS
 };
 
@@ -17,7 +17,6 @@ use cortex_m;
 use cortex_m_rt::entry;
 use rtic::cyccnt::{Instant, U32Ext};
 
-use heapless::Vec;
 use heapless::consts;
 
 #[macro_use]
@@ -70,30 +69,30 @@ macro_rules! add_socket {
 #[entry]
 fn main() -> ! {
 
-	let mut cp = cortex_m::Peripherals::take().unwrap();
+    let mut cp = cortex_m::Peripherals::take().unwrap();
-	let dp = pac::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
 
-	unsafe {
+    unsafe {
-		logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
+        logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
-	}
+    }
-	logger::init();
+    logger::init();
 
     // Enable SRAM3 for the descriptor ring.
     dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
     // // Reset RCC clock
-	// dp.RCC.rsr.write(|w| w.rmvf().set_bit());
+    // dp.RCC.rsr.write(|w| w.rmvf().set_bit());
 
-	let pwr = dp.PWR.constrain();
+    let pwr = dp.PWR.constrain();
-	let vos = pwr.freeze();
+    let vos = pwr.freeze();
 
-	let rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
-	let ccdr = rcc
+    let ccdr = rcc
-		.use_hse(8.mhz())
+        .use_hse(8.mhz())
-		.sys_ck(400.mhz())
+        .sys_ck(400.mhz())
-		.hclk(200.mhz())
+        .hclk(200.mhz())
-		.pll1_q_ck(48.mhz())
+        .pll1_q_ck(48.mhz())
-		.pll1_r_ck(400.mhz())
+        .pll1_r_ck(400.mhz())
-		.freeze(vos, &dp.SYSCFG);
+        .freeze(vos, &dp.SYSCFG);
     
     let delay = cp.SYST.delay(ccdr.clocks);
     
@@ -102,42 +101,42 @@ fn main() -> ! {
 
     cp.DWT.enable_cycle_counter();
 
-	let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
+    let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
-	let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
+    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
-	let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
+    let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
-	let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
+    let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
-	let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
+    let _gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
-	let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
+    let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
     let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
 
     // Note: ITM doesn't work beyond this, due to a pin conflict between:
     // - FPGA_SPI: SCK  (af5)
     // - ST_LINK SWO    (af0)
     // Both demands PB3
-	trace!("Flashing configuration bitstream to iCE40 HX8K on Humpback.");
+    trace!("Flashing configuration bitstream to iCE40 HX8K on Humpback.");
 
-	// Using SPI_1 alternate functions (af5)
+    // Using SPI_1 alternate functions (af5)
-	let fpga_sck = gpiob.pb3.into_alternate_af5();
+    let fpga_sck = gpiob.pb3.into_alternate_af5();
-	let fpga_sdo = gpiob.pb4.into_alternate_af5();
+    let fpga_sdo = gpiob.pb4.into_alternate_af5();
-	let fpga_sdi = gpiob.pb5.into_alternate_af5();
+    let fpga_sdi = gpiob.pb5.into_alternate_af5();
 
-	// Setup SPI_SS_B and CRESET_B
+    // Setup SPI_SS_B and CRESET_B
-	let fpga_ss = gpioa.pa4.into_push_pull_output();
+    let fpga_ss = gpioa.pa4.into_push_pull_output();
-	let fpga_creset = gpiof.pf3.into_open_drain_output();
+    let fpga_creset = gpiof.pf3.into_open_drain_output();
 
-	// Setup CDONE
+    // Setup CDONE
-	let fpga_cdone = gpiod.pd15.into_pull_up_input();
+    let fpga_cdone = gpiod.pd15.into_pull_up_input();
 
-	// Setup SPI interface
+    // Setup SPI interface
-	let fpga_cfg_spi = dp.SPI1.spi(
+    let fpga_cfg_spi = dp.SPI1.spi(
-		(fpga_sck, fpga_sdo, fpga_sdi),
+        (fpga_sck, fpga_sdo, fpga_sdi),
-		spi::MODE_3,
+        spi::MODE_3,
-		12.mhz(),
+        12.mhz(),
-		ccdr.peripheral.SPI1,
+        ccdr.peripheral.SPI1,
-		&ccdr.clocks,
+        &ccdr.clocks,
-	);
+    );
 
-	flash_ice40_fpga(fpga_cfg_spi, fpga_ss, fpga_creset, fpga_cdone, delay).unwrap();
+    flash_ice40_fpga(fpga_cfg_spi, fpga_ss, fpga_creset, fpga_cdone, delay).unwrap();
 
     // Configure ethernet IO
     {
@@ -183,46 +182,45 @@ fn main() -> ! {
         .routes(routes)
         .finalize();
 
-	/*
+    /*
-	 *	Using SPI6
+     *    Using SPI6
-	 *  SCLK -> PA5		(af8)
+     *    SCLK -> PA5        (af8)
-	 *	MOSI -> PG14	(af5)
+     *    MOSI -> PG14       (af5)
-	 *	MISO -> PA6		(af8)
+     *    MISO -> PA6        (af8)
-	 *	CS -> 0: PB12, 1: PA15, 2: PC7
+     *    CS -> 0: PB12, 1: PA15, 2: PC7
-	 */
+     */
-	let sclk = gpioa.pa5.into_alternate_af8().set_speed(Speed::VeryHigh);
+    let sclk = gpioa.pa5.into_alternate_af8().set_speed(Speed::VeryHigh);
-	let mosi = gpiog.pg14.into_alternate_af5().set_speed(Speed::VeryHigh);
+    let mosi = gpiog.pg14.into_alternate_af5().set_speed(Speed::VeryHigh);
-	let miso = gpioa.pa6.into_alternate_af8().set_speed(Speed::VeryHigh);
+    let miso = gpioa.pa6.into_alternate_af8().set_speed(Speed::VeryHigh);
-	let (cs0, cs1, cs2) = (
+    let (cs0, cs1, cs2) = (
-		gpiob.pb12.into_push_pull_output(),
+        gpiob.pb12.into_push_pull_output(),
-		gpioa.pa15.into_push_pull_output(),
+        gpioa.pa15.into_push_pull_output(),
-		gpioc.pc7.into_push_pull_output(),
+        gpioc.pc7.into_push_pull_output(),
-	);
+    );
 
-	/*
+    /*
-	 *	I/O_Update -> PB15
+     *  I/O_Update -> PB15
-	 */
+     */
-	let io_update = gpiob.pb15.into_push_pull_output();
+    let io_update = gpiob.pb15.into_push_pull_output();
 
-	let spi = dp.SPI6.spi(
+    let spi = dp.SPI6.spi(
-		(sclk, miso, mosi),
+        (sclk, miso, mosi),
-		spi::MODE_0,
+        spi::MODE_0,
-		10.mhz(),
+        2.mhz(),
-		ccdr.peripheral.SPI6,
+        ccdr.peripheral.SPI6,
-		&ccdr.clocks,
+        &ccdr.clocks,
-	);
+    );
 
-	let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
+    let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
-	let parts = switch.split();
+    let parts = switch.split();
 
     let mut urukul = Urukul::new(
         parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7
     );
 
-	urukul.reset().unwrap();
+    urukul.reset().unwrap();
-	// info!("Test value: {}", urukul.test().unwrap());
 
-	let mut mqtt_mux = MqttMux::new(urukul);
+    let mut mqtt_mux = MqttMux::new(urukul);
 
     // Time unit in ms
     let mut time: u32 = 0;
@@ -238,9 +236,6 @@ fn main() -> ! {
 
     let tcp_stack = NetworkStack::new(&mut net_interface, sockets);
 
-    // Case dealt: Ethernet connection break down, neither side has timeout
-    // Limitation: Timeout inequality will cause TCP socket state to desync
-    //              Probably fixed in latest smoltcp commit
     let mut client = MqttClient::<consts::U256, _>::new(
         IpAddr::V4(Ipv4Addr::new(192, 168, 1, 125)),
         "Urukul",
@@ -269,9 +264,8 @@ fn main() -> ! {
         // Process MQTT messages about Urukul/Control
         let connection = client
             .poll(|_client, topic, message, _properties| {
-                // info!("On {:?}, received: {:?}", topic, message);
                 // Why is topic a string while message is a slice?
-                mqtt_mux.process_mqtt(topic, message).is_ok();
+                mqtt_mux.process_mqtt(topic, message).unwrap();
             }).is_ok();
         
         if connection && !has_subscribed && tick {

src/nal_tcp_client.rs

@@ -56,7 +56,7 @@ impl<'a, 'b, 'c, 'n> NetworkStack<'a, 'b, 'c, 'n> {
         self.network_interface.poll_delay(
             &mut self.sockets.borrow_mut(),
             net::time::Instant::from_millis(time as i64),
-        ).map_or(1000, |next_poll_time| next_poll_time.total_millis() as u32)
+        ).map_or(0, |next_poll_time| next_poll_time.total_millis() as u32)
     }
 
     pub fn update(&mut self, time: u32) -> bool {
@@ -120,6 +120,8 @@ impl<'a, 'b, 'c, 'n> embedded_nal::TcpStack for NetworkStack<'a, 'b, 'c, 'n> {
                 internal_socket
                     .connect((address, remote.port()), self.get_ephemeral_port())
                     .map_err(|_| NetworkError::ConnectionFailure)?;
+                internal_socket
+                    .set_keep_alive(Some(net::time::Duration::from_millis(1000)));
             }
             embedded_nal::IpAddr::V6(addr) => {
                 let address = {
@@ -132,6 +134,8 @@ impl<'a, 'b, 'c, 'n> embedded_nal::TcpStack for NetworkStack<'a, 'b, 'c, 'n> {
                 internal_socket
                     .connect((address, remote.port()), self.get_ephemeral_port())
                     .map_err(|_| NetworkError::ConnectionFailure)?;
+                internal_socket
+                    .set_keep_alive(Some(net::time::Duration::from_millis(1000)));
             }
         };
 

src/spi_slave.rs

@@ -1,61 +1,61 @@
 use embedded_hal::{
-	blocking::spi::Transfer,
+    blocking::spi::Transfer,
-	digital::v2::OutputPin,
+    digital::v2::OutputPin,
 };
 use crate::cpld::CPLD;
 use crate::urukul::Error;
 
 pub struct SPISlave<'a, SPI, CS0, CS1, CS2, GPIO> (
-	// SPI device to be multiplexed
+    // SPI device to be multiplexed
-	&'a CPLD<SPI, CS0, CS1, CS2, GPIO>,
+    &'a CPLD<SPI, CS0, CS1, CS2, GPIO>,
-	// Channel of SPI slave
+    // Channel of SPI slave
-	u8,
+    u8,
-	// Need I/O Update
+    // Need I/O Update
-	bool,
+    bool,
 );
 
 pub struct Parts<'a, SPI, CS0, CS1, CS2, GPIO> {
-	pub spi1: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi1: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
-	pub spi2: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi2: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
-	pub spi3: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi3: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
-	pub spi4: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi4: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
-	pub spi5: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi5: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
-	pub spi6: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi6: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
-	pub spi7: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
+    pub spi7: SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>,
 }
 
 impl<'a, SPI, CS0, CS1, CS2, GPIO> Parts<'a, SPI, CS0, CS1, CS2, GPIO> {
-	pub(crate) fn new(cpld: &'a CPLD<SPI, CS0, CS1, CS2, GPIO>) -> Self {
+    pub(crate) fn new(cpld: &'a CPLD<SPI, CS0, CS1, CS2, GPIO>) -> Self {
-		Parts {
+        Parts {
-			spi1: SPISlave(&cpld, 1, false),
+            spi1: SPISlave(&cpld, 1, false),
-			spi2: SPISlave(&cpld, 2, false),
+            spi2: SPISlave(&cpld, 2, false),
-			spi3: SPISlave(&cpld, 3, false),
+            spi3: SPISlave(&cpld, 3, false),
-			spi4: SPISlave(&cpld, 4, true),
+            spi4: SPISlave(&cpld, 4, true),
-			spi5: SPISlave(&cpld, 5, true),
+            spi5: SPISlave(&cpld, 5, true),
-			spi6: SPISlave(&cpld, 6, true),
+            spi6: SPISlave(&cpld, 6, true),
-			spi7: SPISlave(&cpld, 7, true),
+            spi7: SPISlave(&cpld, 7, true),
-		}
+        }
-	}
+    }
 }
 
 impl<'a, SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for SPISlave<'a, SPI, CS0, CS1, CS2, GPIO>
 where
-	CS2: OutputPin,
+    CS2: OutputPin,
-	CS1: OutputPin,
+    CS1: OutputPin,
-	CS0: OutputPin,
+    CS0: OutputPin,
-	SPI: Transfer<u8, Error = E>,
+    SPI: Transfer<u8, Error = E>,
-	GPIO: OutputPin,
+    GPIO: OutputPin,
 {
-	type Error = Error<E>;
+    type Error = Error<E>;
 
-	fn transfer<'w>(&mut self, words: &'w mut[u8]) -> Result<&'w [u8], Self::Error> {
+    fn transfer<'w>(&mut self, words: &'w mut[u8]) -> Result<&'w [u8], Self::Error> {
-		let mut dev = self.0.data.try_borrow_mut().map_err(|_| Error::GetRefMutDataError)?;
+        let mut dev = self.0.data.try_borrow_mut().map_err(|_| Error::GetRefMutDataError)?;
-		dev.select_chip(self.1).map_err(|_| Error::CSError)?;
+        dev.select_chip(self.1).map_err(|_| Error::CSError)?;
-		let result = dev.spi.transfer(words).map_err(Error::SPI)?;
+        let result = dev.spi.transfer(words).map_err(Error::SPI)?;
-		dev.select_chip(0).map_err(|_| Error::CSError)?;
+        dev.select_chip(0).map_err(|_| Error::CSError)?;
-		if self.2 {
+        if self.2 {
-			dev.issue_io_update().map_err(|_| Error::IOUpdateError)?;
+            dev.issue_io_update().map_err(|_| Error::IOUpdateError)?;
-		}
+        }
-		Ok(result)
+        Ok(result)
-	}
+    }
 }

src/urukul.rs

@@ -1,338 +1,346 @@
 extern crate embedded_hal;
 use embedded_hal::{
-	blocking::spi::Transfer,
+    blocking::spi::Transfer,
 };
 
 use crate::config_register::ConfigRegister;
 use crate::config_register::CFGMask;
 use crate::config_register::StatusMask;
 use crate::attenuator::Attenuator;
-use crate::dds::DDS;
+use crate::dds::{ DDS, RAMOperationMode };
 
 /*
- *	Enum for structuring error
+ * Enum for structuring error
  */
 #[derive(Debug)]
 pub enum Error<E> {
-	SPI(E),
+    SPI(E),
-	CSError,
+    CSError,
-	GetRefMutDataError,
+    GetRefMutDataError,
-	AttenuatorError,
+    AttenuatorError,
-	IOUpdateError,
+    IOUpdateError,
-	DDSError,
+    DDSError,
-	ConfigRegisterError,
+    ConfigRegisterError,
-	DDSCLKError,
+    DDSCLKError,
-	DDSRAMError,
+    DDSRAMError,
-	ParameterError,
+    ParameterError,
-	MqttTopicError,
+    MqttTopicError,
-	MqttCommandError,
+    MqttCommandError,
 }
 
 #[derive(Debug, Clone)]
 pub enum ClockSource {
-	OSC,
+    OSC,
-	SMA,
+    SMA,
-	MMCX,
+    MMCX,
 }
 
 /*
  *  Struct for Urukul master device
  */
 pub struct Urukul<SPI> {
-	config_register: ConfigRegister<SPI>,
+    config_register: ConfigRegister<SPI>,
-	attenuator: Attenuator<SPI>,
+    attenuator: Attenuator<SPI>,
-	multi_dds: DDS<SPI>,
+    multi_dds: DDS<SPI>,
-	dds: [DDS<SPI>; 4],
+    dds: [DDS<SPI>; 4],
-	f_master_clk: f64,
+    f_master_clk: f64,
 }
 
 impl<SPI, E> Urukul<SPI>
 where
-	SPI: Transfer<u8, Error = E>,
+    SPI: Transfer<u8, Error = E>,
 {
-	/*
+    /*
-	 *  Master constructor for the entire Urukul device
+     *  Master constructor for the entire Urukul device
-	 *  Supply 7 SPI channels to Urukul and 4 reference clock frequencies
+     *  Supply 7 SPI channels to Urukul and 4 reference clock frequencies
-	 */
+     */
-	pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI) -> Self {
+    pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI) -> Self {
-		// Construct Urukul
+        // Construct Urukul
-		Urukul {
+        Urukul {
-			config_register: ConfigRegister::new(spi1),
+            config_register: ConfigRegister::new(spi1),
-			attenuator: Attenuator::new(spi2),
+            attenuator: Attenuator::new(spi2),
-			// Create a multi-channel DDS with predefined 25MHz clock
+            // Create a multi-channel DDS with predefined 25MHz clock
-			multi_dds: DDS::new(spi3, 25_000_000.0),
+            multi_dds: DDS::new(spi3, 25_000_000.0),
-			// Create 4 DDS instances with predefined 25MHz clock
+            // Create 4 DDS instances with predefined 25MHz clock
-			// Counter-intuitive to assign urukul clock before having a urukul
+            // Counter-intuitive to assign urukul clock before having a urukul
-			dds: [
+            dds: [
-				DDS::new(spi4, 25_000_000.0),
+                DDS::new(spi4, 25_000_000.0),
-				DDS::new(spi5, 25_000_000.0),
+                DDS::new(spi5, 25_000_000.0),
-				DDS::new(spi6, 25_000_000.0),
+                DDS::new(spi6, 25_000_000.0),
-				DDS::new(spi7, 25_000_000.0),
+                DDS::new(spi7, 25_000_000.0),
-			],
+            ],
-			// Default clock selection: OSC, predefined 100MHz speed
+            // Default clock selection: OSC, predefined 100MHz speed
-			f_master_clk: 100_000_000.0,
+            f_master_clk: 100_000_000.0,
-		}
+        }
-	}
+    }
 
-	/*
+    /*
-	 *  Reset method. To be invoked by initialization and manual reset.
+     *  Reset method. To be invoked by initialization and manual reset.
-	 *  Only Urukul struct provides reset method.
+     *  Only Urukul struct provides reset method.
-	 *  DDS reset is controlled by Urukul (RST).
+     *  DDS reset is controlled by Urukul (RST).
-	 *  Attenuators only have shift register reset, which does not affect its data
+     *  Attenuators only have shift register reset, which does not affect its data
-	 *  CPLD only has a "all-zero" default state.
+     *  CPLD only has a "all-zero" default state.
-	 */
+     */
-	pub fn reset(&mut self) -> Result<(), Error<E>> {
+    pub fn reset(&mut self) -> Result<(), Error<E>> {
-		// Reset DDS and attenuators
+        // Reset DDS and attenuators
-		self.config_register.set_configurations(&mut [
+        self.config_register.set_configurations(&mut [
-			(CFGMask::RST, 1),
+            (CFGMask::RST, 1),
-			(CFGMask::IO_RST, 1),
+            (CFGMask::IO_RST, 1),
-			(CFGMask::IO_UPDATE, 0)
+            (CFGMask::IO_UPDATE, 0)
-		])?;
+        ])?;
-		// Set 0 to all fields on configuration register.
+        // Set 0 to all fields on configuration register.
-		self.config_register.set_configurations(&mut [
+        self.config_register.set_configurations(&mut [
-			(CFGMask::RF_SW, 		0),
+            (CFGMask::RF_SW,        0),
-			(CFGMask::LED, 			0),
+            (CFGMask::LED,          0),
-			(CFGMask::PROFILE, 		0),
+            (CFGMask::PROFILE,      0),
-			(CFGMask::IO_UPDATE, 	0),
+            (CFGMask::IO_UPDATE,    0),
-			(CFGMask::MASK_NU, 		0),
+            (CFGMask::MASK_NU,      0),
-			(CFGMask::CLK_SEL0, 	0),
+            (CFGMask::CLK_SEL0,     0),
-			(CFGMask::SYNC_SEL, 	0),
+            (CFGMask::SYNC_SEL,     0),
-			(CFGMask::RST, 			0),
+            (CFGMask::RST,          0),
-			(CFGMask::IO_RST, 		0),
+            (CFGMask::IO_RST,       0),
-			(CFGMask::CLK_SEL1, 	0),
+            (CFGMask::CLK_SEL1,     0),
-			(CFGMask::DIV, 			0),
+            (CFGMask::DIV,          0),
-		])?;
+        ])?;
-		// Init all DDS chips. Configure SDIO as input only.
+        // Init all DDS chips. Configure SDIO as input only.
-		for chip_no in 0..4 {
+        for chip_no in 0..4 {
-			self.dds[chip_no].init()?;
+            self.dds[chip_no].init()?;
-		}
+        }
-		// Clock tree reset. OSC clock source by default
+        // Clock tree reset. OSC clock source by default
-		self.f_master_clk = 100_000_000.0;
+        self.f_master_clk = 100_000_000.0;
-		// CPLD divides clock frequency by 4 by default.
+        // CPLD divides clock frequency by 4 by default.
-		for chip_no in 0..4 {
+        for chip_no in 0..4 {
-			self.dds[chip_no].set_ref_clk_frequency(self.f_master_clk / 4.0)?;
+            self.dds[chip_no].set_ref_clk_frequency(self.f_master_clk / 4.0)?;
-		}
+        }
-		Ok(())
+        Ok(())
-	}
+    }
 
-	/*
+    /*
-	 *  Test method fo Urukul.
+     *  Test method fo Urukul.
-	 *  Return the number of test failed.
+     *  Return the number of test failed.
-	 */
+     */
-	pub fn test(&mut self) -> Result<u32, Error<E>> {
+    pub fn test(&mut self) -> Result<u32, Error<E>> {
-		let mut count = self.config_register.test()?;
+        let mut count = self.config_register.test()?;
-		count += self.attenuator.test()?;
+        count += self.attenuator.test()?;
-		for chip_no in 0..4 {
+        for chip_no in 0..4 {
-			count += self.dds[chip_no].test()?;
+            count += self.dds[chip_no].test()?;
-		}
+        }
-		Ok(count)
+        Ok(count)
-	}
+    }
 }
 
 impl<SPI, E> Urukul<SPI>
 where
-	SPI: Transfer<u8, Error = E>
+    SPI: Transfer<u8, Error = E>
 {
 
-	pub fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Error<E>> {
+    pub fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Error<E>> {
-		if channel < 4 {
+        if channel < 4 {
-			self.config_register.get_status(StatusMask::RF_SW).map(|val| (val & (1 << channel)) != 0)
+            self.config_register.get_status(StatusMask::RF_SW).map(|val| (val & (1 << channel)) != 0)
-		} else {
+        } else {
-			Err(Error::ParameterError)
+            Err(Error::ParameterError)
-		}
+        }
-	}
+    }
 
-	pub fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Error<E>> {
+    pub fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Error<E>> {
-		if channel < 4 {
+        if channel < 4 {
-			let prev = u32::from(self.config_register.get_status(StatusMask::RF_SW)?);
+            let prev = u32::from(self.config_register.get_status(StatusMask::RF_SW)?);
-			let next = {
+            let next = {
-				if status {
+                if status {
-					prev | (1 << channel)
+                    prev | (1 << channel)
-				} else {
+                } else {
-					prev & (!(1 << channel))
+                    prev & (!(1 << channel))
-				}
+                }
-			};
+            };
-			self.config_register.set_configurations(&mut [
+            self.config_register.set_configurations(&mut [
-				(CFGMask::RF_SW, next),
+                (CFGMask::RF_SW, next),
-			]).map(|_| ())
+            ]).map(|_| ())
-		} else {
+        } else {
-			Err(Error::ParameterError)
+            Err(Error::ParameterError)
-		}
+        }
-	}
+    }
 
-	pub fn set_clock(&mut self, source: ClockSource, frequency: f64, division: u8) -> Result<(), Error<E>> {
+    pub fn set_clock(&mut self, source: ClockSource, frequency: f64, division: u8) -> Result<(), Error<E>> {
-		// Change clock source through configuration register
+        // Change clock source through configuration register
-		self.set_clock_source(source)?;
+        self.set_clock_source(source)?;
 
-		// Modify the master clock frequency
+        // Modify the master clock frequency
-		// Prevent redundunt call to change f_ref_clk
+        // Prevent redundunt call to change f_ref_clk
-		self.f_master_clk = frequency;
+        self.f_master_clk = frequency;
 
-		self.set_clock_division(division)
+        self.set_clock_division(division)
-	}
+    }
 
-	pub fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
+    pub fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
-		// Change clock source through configuration register
+        // Change clock source through configuration register
-		match source {
+        match source {
-			ClockSource::OSC => self.config_register.set_configurations(&mut [
+            ClockSource::OSC => self.config_register.set_configurations(&mut [
-				(CFGMask::CLK_SEL0, 0),
+                (CFGMask::CLK_SEL0, 0),
-				(CFGMask::CLK_SEL1, 0),
+                (CFGMask::CLK_SEL1, 0),
-			]),
+            ]),
-			ClockSource::MMCX => self.config_register.set_configurations(&mut [
+            ClockSource::MMCX => self.config_register.set_configurations(&mut [
-				(CFGMask::CLK_SEL0, 0),
+                (CFGMask::CLK_SEL0, 0),
-				(CFGMask::CLK_SEL1, 1),
+                (CFGMask::CLK_SEL1, 1),
-			]),
+            ]),
-			ClockSource::SMA => self.config_register.set_configurations(&mut [
+            ClockSource::SMA => self.config_register.set_configurations(&mut [
-				(CFGMask::CLK_SEL0, 1),
+                (CFGMask::CLK_SEL0, 1),
-			]),
+            ]),
-		}.map(|_| ())
+        }.map(|_| ())
-	}
+    }
 
-	pub fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
+    pub fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
-		// Update master clock frequency
+        // Update master clock frequency
-		self.f_master_clk = frequency;
+        self.f_master_clk = frequency;
 
-		// Update all DDS f_ref_clk
+        // Update all DDS f_ref_clk
-		self.set_dds_ref_clk()
+        self.set_dds_ref_clk()
-	}
+    }
 
-	pub fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
+    pub fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
-		match division {
+        match division {
-			1 => self.config_register.set_configurations(&mut [
+            1 => self.config_register.set_configurations(&mut [
-				(CFGMask::DIV, 1),
+                (CFGMask::DIV, 1),
-			]),
+            ]),
-			2 => self.config_register.set_configurations(&mut [
+            2 => self.config_register.set_configurations(&mut [
-				(CFGMask::DIV, 2),
+                (CFGMask::DIV, 2),
-			]),
+            ]),
-			4 => self.config_register.set_configurations(&mut [
+            4 => self.config_register.set_configurations(&mut [
-				(CFGMask::DIV, 3),
+                (CFGMask::DIV, 3),
-			]),
+            ]),
-			_ => Err(Error::ParameterError),
+            _ => Err(Error::ParameterError),
-		}?;
+        }?;
 
-		self.set_dds_ref_clk()
+        self.set_dds_ref_clk()
-	}
+    }
 
-	fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
+    fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
-		// Calculate reference clock frequency after clock division from configuration register
+        // Calculate reference clock frequency after clock division from configuration register
-		let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
+        let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
 
-		// Update all DDS chips on reference clock frequency
+        // Update all DDS chips on reference clock frequency
-		for dds_channel in 0..4 {
+        for dds_channel in 0..4 {
-			self.dds[dds_channel].set_ref_clk_frequency(f_ref_clk)?;
+            self.dds[dds_channel].set_ref_clk_frequency(f_ref_clk)?;
-		}
+        }
-		Ok(())
+        Ok(())
-	}
+    }
 
-	fn get_master_clock_division(&mut self) -> u8 {
+    fn get_master_clock_division(&mut self) -> u8 {
-		match self.config_register.get_configuration(CFGMask::DIV) {
+        match self.config_register.get_configuration(CFGMask::DIV) {
-			0 | 3 => 4,
+            0 | 3 => 4,
-			1 => 1,
+            1 => 1,
-			2 => 2,
+            2 => 2,
-			_ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
+            _ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
-		}
+        }
-	}
+    }
 
-	pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
+    pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
-		if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
+        if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
-			return Err(Error::ParameterError);
+            return Err(Error::ParameterError);
-		}
+        }
-		self.attenuator.set_channel_attenuation(channel, attenuation)
+        self.attenuator.set_channel_attenuation(channel, attenuation)
-	}
+    }
 
-	pub fn set_profile(&mut self, profile: u8) -> Result<(), Error<E>> {
+    pub fn set_profile(&mut self, profile: u8) -> Result<(), Error<E>> {
-		if profile >= 8 {
+        if profile >= 8 {
-			return Err(Error::ParameterError);
+            return Err(Error::ParameterError);
-		}
+        }
-		self.config_register.set_configurations(&mut [
+        self.config_register.set_configurations(&mut [
-			(CFGMask::PROFILE, profile.into())
+            (CFGMask::PROFILE, profile.into())
-		]).map(|_| ())
+        ]).map(|_| ())
-	}
+    }
 
-	pub fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
+    pub fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
-		if channel >= 4 || profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
+        if channel >= 4 || profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
-			phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
+            phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
-			return Err(Error::ParameterError);
+            return Err(Error::ParameterError);
-		}
+        }
-		self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
+        self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
-	}
+    }
 
-	pub fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Error<E>> {
+    pub fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Error<E>> {
-		if channel >= 4 || profile >= 8 || frequency < 0.0 {
+        if channel >= 4 || profile >= 8 || frequency < 0.0 {
-			return Err(Error::ParameterError);
+            return Err(Error::ParameterError);
-		}
+        }
-		self.dds[usize::from(channel)].set_single_tone_profile_frequency(profile, frequency)
+        self.dds[usize::from(channel)].set_single_tone_profile_frequency(profile, frequency)
-	}
+    }
 
-	pub fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Error<E>> {
+    pub fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Error<E>> {
-		if channel >= 4 || profile >= 8 || phase >= 360.0 || phase < 0.0 {
+        if channel >= 4 || profile >= 8 || phase >= 360.0 || phase < 0.0 {
-			return Err(Error::ParameterError);
+            return Err(Error::ParameterError);
-		}
+        }
-		self.dds[usize::from(channel)].set_single_tone_profile_phase(profile, phase)
+        self.dds[usize::from(channel)].set_single_tone_profile_phase(profile, phase)
-	}
+    }
 
-	pub fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Error<E>> {
+    pub fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Error<E>> {
-		if channel >= 4 || profile >= 8 || amplitude < 0.0 || amplitude > 1.0 {
+        if channel >= 4 || profile >= 8 || amplitude < 0.0 || amplitude > 1.0 {
-			return Err(Error::ParameterError);
+            return Err(Error::ParameterError);
-		}
+        }
-		self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
+        self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
-	}
+    }
 
-	pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
+    pub fn set_channel_frequency_sweep_profile(&mut self, channel: u8, profile: u8, start_addr: u16, lower_boundary: f64,
-		self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ())
+        upper_boundary: f64, f_resolution: f64, playback_rate: f64) -> Result<(), Error<E>>
-	}
+    {
+        unsafe {
+            self.dds[usize::from(channel)]
+                .set_frequency_sweep_profile(profile, start_addr, lower_boundary, upper_boundary,
+                f_resolution, true, RAMOperationMode::ContinuousRecirculate, playback_rate)
+        }
+    }
 
-	// Multi-dds channel functions
+    pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
-	// Do not allow reading of DDS registers
+        self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ())
-	// Make sure only 1 SPI transaction is compelted per function call
+    }
 
-	// Setup NU_MASK in configuration register
+    // Multi-dds channel functions
-	// This selects the DDS channels that will be covered by multi_channel DDS (spi3)
+    // Do not allow reading of DDS registers
-	// Note: If a channel is masked, io_update must be completed through configuration register (IO_UPDATE bit-field)
+    // Make sure only 1 SPI transaction is compelted per function call
-	// Implication: Deselect such channel if individual communication is needed.
-	pub fn set_multi_channel_coverage(&mut self, channel: u8) -> Result<(), Error<E>> {
-		self.config_register.set_configurations(&mut [
-			(CFGMask::MASK_NU, channel.into())
-		]).map(|_| ())
-	}
 
-	// Difference from individual single tone setup function:
+    // Setup NU_MASK in configuration register
-	// - Remove the need of passing channel
+    // This selects the DDS channels that will be covered by multi_channel DDS (spi3)
-	// All selected channels must share the same f_sys_clk
+    // Note: If a channel is masked, io_update must be completed through configuration register (IO_UPDATE bit-field)
-	pub fn set_multi_channel_single_tone_profile(&mut self, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
+    // Implication: Deselect such channel if individual communication is needed.
-		if profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
+    pub fn set_multi_channel_coverage(&mut self, channel: u8) -> Result<(), Error<E>> {
-			phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
+        self.config_register.set_configurations(&mut [
-			return Err(Error::ParameterError);
+            (CFGMask::MASK_NU, channel.into())
-		}
+        ]).map(|_| ())
-		// Check f_sys_clk of all selected channels
+    }
-		let selected_channels = self.config_register.get_configuration(CFGMask::MASK_NU);
-		let mut found_a_selected_channel = false;
-		let mut reported_f_sys_clk: f64 = 0.0;
-		for channel_bit in 0..4 {
-			if (selected_channels & (1 << (channel_bit as u8))) != 0 {
-				if !found_a_selected_channel {
-					found_a_selected_channel = true;
-					reported_f_sys_clk = self.dds[channel_bit].get_f_sys_clk();
-				} else if reported_f_sys_clk != self.dds[channel_bit].get_f_sys_clk() {
-					return Err(Error::DDSError);
-				}
-			}
-		}
-		self.multi_dds.set_sys_clk_frequency(reported_f_sys_clk);
-		self.multi_dds.set_single_tone_profile(profile, frequency, phase, amplitude)?;
-		self.invoke_io_update()?;
-		Ok(())
-	}
 
-	// Generate a pulse for io_update bit in configuration register
+    // Difference from individual single tone setup function:
-	// This acts like io_update in CPLD struct, but for multi-dds channel
+    // - Remove the need of passing channel
-	fn invoke_io_update(&mut self) -> Result<(), Error<E>> {
+    // All selected channels must share the same f_sys_clk
-		self.config_register.set_configurations(&mut [
+    pub fn set_multi_channel_single_tone_profile(&mut self, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
-			(CFGMask::IO_UPDATE, 1)
+        if profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
-		])?;
+            phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
-		self.config_register.set_configurations(&mut [
+            return Err(Error::ParameterError);
-			(CFGMask::IO_UPDATE, 0)
+        }
-		]).map(|_| ())
+        // Check f_sys_clk of all selected channels
-	}
+        let selected_channels = self.config_register.get_configuration(CFGMask::MASK_NU);
+        let mut found_a_selected_channel = false;
+        let mut reported_f_sys_clk: f64 = 0.0;
+        for channel_bit in 0..4 {
+            if (selected_channels & (1 << (channel_bit as u8))) != 0 {
+                if !found_a_selected_channel {
+                    found_a_selected_channel = true;
+                    reported_f_sys_clk = self.dds[channel_bit].get_f_sys_clk();
+                } else if reported_f_sys_clk != self.dds[channel_bit].get_f_sys_clk() {
+                    return Err(Error::DDSError);
+                }
+            }
+        }
+        self.multi_dds.set_sys_clk_frequency(reported_f_sys_clk)?;
+        self.multi_dds.set_single_tone_profile(profile, frequency, phase, amplitude)?;
+        self.invoke_io_update()
+    }
 
+    // Generate a pulse for io_update bit in configuration register
+    // This acts like io_update in CPLD struct, but for multi-dds channel
+    fn invoke_io_update(&mut self) -> Result<(), Error<E>> {
+        self.config_register.set_configurations(&mut [
+            (CFGMask::IO_UPDATE, 1)
+        ])?;
+        self.config_register.set_configurations(&mut [
+            (CFGMask::IO_UPDATE, 0)
+        ]).map(|_| ())
+    }
 }