From fa117c94bb1691343a28d68d0ce3a1bfe73463cc Mon Sep 17 00:00:00 2001 From: occheung Date: Thu, 27 Aug 2020 17:09:35 +0800 Subject: [PATCH] ethernet: separate pin dec --- .cargo/config | 2 +- Cargo.toml | 1 + examples/ethernet.rs | 43 +++++++++++++----- src/main.rs | 101 +++++++++++++++++++++++++++---------------- 4 files changed, 98 insertions(+), 49 deletions(-) diff --git a/.cargo/config b/.cargo/config index c0ce242..86b3292 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = "gdb -q -x gdb_config/fpga_config.gdb" +runner = "gdb -q -x gdb_config/openocd.gdb" rustflags = [ "-C", "link-arg=-Tlink.x", ] diff --git a/Cargo.toml b/Cargo.toml index 5ae1074..6693209 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,6 +11,7 @@ panic-halt = "0.2.0" cortex-m = "0.6.2" cortex-m-rt = "0.6.12" embedded-hal = "0.2.4" +stm32h7 = {version = "0.11.0"} stm32h7xx-hal = {version = "0.6.0", features = [ "stm32h743v", "rt", "unproven" ] } stm32h7-ethernet = { version = "0.2.0", features = [ "phy_lan8742a", "stm32h743v" ] } smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-raw" ] } diff --git a/examples/ethernet.rs b/examples/ethernet.rs index b2b2cb4..dd08bc4 100644 --- a/examples/ethernet.rs +++ b/examples/ethernet.rs @@ -19,6 +19,8 @@ use cortex_m_rt::{ use cortex_m_semihosting::hprintln; extern crate smoltcp; + +// Ethernet crate for STM32H7 has been merged into HAL in the latest commit extern crate stm32h7_ethernet as ethernet; use stm32h7xx_hal::gpio::Speed; @@ -48,7 +50,6 @@ use core::mem::uninitialized; use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr}; use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder}; use smoltcp::socket::SocketSet; -//use smoltcp::socket::{UdpSocket, UdpSocketBuffer, UdpPacketMetadata}; use smoltcp::socket::{SocketHandle, TcpSocket, TcpSocketBuffer}; use smoltcp::time::{Duration, Instant}; @@ -132,15 +133,11 @@ fn main() -> ! { status_led.set_low().ok(); listen_led.set_low().ok(); - let _rmii_ref_clk = gpioa.pa1.into_alternate_af11().set_speed(VeryHigh); - let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(VeryHigh); - let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(VeryHigh); - let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(VeryHigh); - let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(VeryHigh); - let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(VeryHigh); - let _rmii_tx_en = gpiog.pg11.into_alternate_af11().set_speed(VeryHigh); - let _rmii_txd0 = gpiog.pg13.into_alternate_af11().set_speed(VeryHigh); - let _rmii_txd1 = gpiob.pb13.into_alternate_af11().set_speed(VeryHigh); + // Setup ethernet pins + setup_ethernet_pins( + gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7, gpioc.pc4, + gpioc.pc5, gpiog.pg11, gpiog.pg13, gpiob.pb13 + ); // Initialise ethernet... assert_eq!(ccdr.clocks.hclk().0, 200_000_000); // HCLK 200MHz @@ -304,6 +301,32 @@ fn main() -> ! { } } +use stm32h7xx_hal::gpio::{ + gpioa::{PA1, PA2, PA7}, + gpiob::{PB13}, + gpioc::{PC1, PC4, PC5}, + gpiog::{PG11, PG13}, + Speed::VeryHigh, +}; + +/* + * Migrated ethernet setup pins + */ +pub fn setup_ethernet_pins( + pa1: PA1, pa2: PA2, pc1: PC1, pa7: PA7, pc4: PC4, + pc5: PC5, pg11: PG11, pg13: PG13, pb13: PB13 +) { + pa1.into_alternate_af11().set_speed(VeryHigh); + pa2.into_alternate_af11().set_speed(VeryHigh); + pc1.into_alternate_af11().set_speed(VeryHigh); + pa7.into_alternate_af11().set_speed(VeryHigh); + pc4.into_alternate_af11().set_speed(VeryHigh); + pc5.into_alternate_af11().set_speed(VeryHigh); + pg11.into_alternate_af11().set_speed(VeryHigh); + pg13.into_alternate_af11().set_speed(VeryHigh); + pb13.into_alternate_af11().set_speed(VeryHigh); +} + #[interrupt] fn ETH() { unsafe { ethernet::interrupt_handler() } diff --git a/src/main.rs b/src/main.rs index b9c338a..2541b54 100644 --- a/src/main.rs +++ b/src/main.rs @@ -119,52 +119,77 @@ fn main() -> ! { dds0.set_configurations(&mut [ (DDSCFRMask::PDCLK_ENABLE, 0), (DDSCFRMask::READ_EFFECTIVE_FTW, 1), - (DDSCFRMask::DIGITAL_RAMP_ENABLE, 0), - (DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1), ]).unwrap(); - dds0.enable_pll(1_150_000_000).unwrap(); - - hprintln!("{:#X?}", dds0.read_register(0x02, &mut[ - 0x00, 0x00, 0x00, 0x00 - ]).unwrap()).unwrap(); - - // Calculate FTW - let f_out = 10_000_000; - let f_sclk = 1_150_000_000; - let resolution :u64 = 1 << 32; - let ftw = (resolution * f_out / f_sclk) as u32; - - // Read single-tone profile 0 - let mut profile :[u8; 8] = [0; 8]; - dds0.read_register(0x0E, &mut profile).unwrap(); - - // Overwrite FTW on profile 0 - profile[0] = 0x1F; - profile[1] = 0xFF; - profile[4] = ((ftw >> 24) & 0xFF) as u8; - profile[5] = ((ftw >> 16) & 0xFF) as u8; - profile[6] = ((ftw >> 8 ) & 0xFF) as u8; - profile[7] = ((ftw >> 0 ) & 0xFF) as u8; - - dds0.write_register(0x0E, &mut profile).unwrap(); - hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap(); + dds0.enable_pll(1_000_000_000).unwrap(); // Attenuator att.set_attenuation([ 0.0, 31.5, 24.0, 0.0 ]).unwrap(); - hprintln!("{:#X?}", dds0.get_configurations(&mut - [ - (DDSCFRMask::SDIO_IN_ONLY, 0), - (DDSCFRMask::LSB_FIRST, 0), - (DDSCFRMask::PROFILE_CTRL, 0), - (DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 0), - (DDSCFRMask::DRV0, 0), - (DDSCFRMask::VCO_SEL, 0) - ] - ).unwrap()).unwrap(); + dds0.set_single_tone_profile(1, 10_000_000, 0.0, 0.5).unwrap(); + config.set_configurations(&mut [ + (CFGMask::PROFILE, 1), + ]).unwrap(); + + // Setup RAM configuration + dds0.set_configurations(&mut [ + (DDSCFRMask::RAM_ENABLE, 1), + (DDSCFRMask::RAM_PLAYBACK_DST, 2), + ]).unwrap(); + + // Configure RAM profile 0 + dds0.write_register(0x0E, &mut [ + 0x00, // Open + 0x09, 0xC4, // Address step rate (2500) + 0xFF, 0xC0, // End at address 1023 + 0x00, 0x00, // Start at address 0 + 0x04, // Recirculate mode + ]).unwrap(); + + hprintln!("{:#X?}", dds0.read_register(0x0E, &mut[ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + ]).unwrap()).unwrap(); + + // Choose profile 0 + config.set_configurations(&mut [ + (CFGMask::PROFILE, 0), + ]).unwrap(); + + // Set RAM to be amplitudes, disable RAM momentarily + dds0.set_configurations(&mut [ + (DDSCFRMask::RAM_PLAYBACK_DST, 0), + (DDSCFRMask::RAM_ENABLE, 0), + ]).unwrap(); + + let mut ram_data: [u8; ((1024 * 4) + 1)] = [0; (1024 * 4) + 1]; + ram_data[0] = 0x16; + for index in 0..1024 { + if index % 2 == 1 { + ram_data[(index * 4) + 1] = 0x3F; + ram_data[(index * 4) + 2] = 0xFF; + } else { + ram_data[(index * 4) + 1] = 0x00; + ram_data[(index * 4) + 2] = 0x00; + } + // ram_data[(index * 4) + 1] = ((index >> 2) & 0xFF) as u8; + // ram_data[(index * 4) + 2] = ((index & 0x03) << 6) as u8; + } + dds0.transfer(&mut ram_data).unwrap(); + + config.set_configurations(&mut [ + (CFGMask::PROFILE, 1), + ]).unwrap(); + + config.set_configurations(&mut [ + (CFGMask::PROFILE, 0), + ]).unwrap(); + + dds0.set_configurations(&mut [ + (DDSCFRMask::RAM_ENABLE, 1), + ]).unwrap(); loop {} }