From eaaee84fbcaec5e7fd6bc38a21e870f70108bbcc Mon Sep 17 00:00:00 2001 From: occheung Date: Thu, 10 Sep 2020 16:22:12 +0800 Subject: [PATCH] itm: enable itm logging --- examples/tcp_client.rs | 26 +++++++++++++++++++------- examples/util/logger.rs | 6 +++--- gdb_config/debug.gdb | 4 +++- gdb_config/openocd.gdb | 6 +++--- 4 files changed, 28 insertions(+), 14 deletions(-) diff --git a/examples/tcp_client.rs b/examples/tcp_client.rs index c420027..54c3340 100644 --- a/examples/tcp_client.rs +++ b/examples/tcp_client.rs @@ -30,6 +30,7 @@ use cortex_m_rt::{ // use cortex_m_semihosting::hprintln; // use panic_halt as _; +use panic_itm as _; use rtic::cyccnt::{Instant, U32Ext}; @@ -83,14 +84,20 @@ fn main() -> ! { let ccdr = rcc .use_hse(8.mhz()) .sysclk(400.mhz()) - // .hclk(200.mhz()) - // .per_ck(100.mhz()) + .hclk(200.mhz()) + .per_ck(100.mhz()) .pll1_q_ck(48.mhz()) // for SPI - // .pll1_r_ck(400.mhz()) // for TRACECK - // .pll2_p_ck(100.mhz()) - // .pll2_q_ck(100.mhz()) + .pll1_r_ck(400.mhz()) // for TRACECK + .pll2_p_ck(100.mhz()) + .pll2_q_ck(100.mhz()) .freeze(vos, &dp.SYSCFG); + // info!("{}", ccdr.clocks.c_ck().0); + + unsafe { + logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM); + } + let mut delay = cp.SYST.delay(ccdr.clocks); let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA); @@ -108,6 +115,10 @@ fn main() -> ! { let mut green_led = gpiob.pb0.into_push_pull_output(); green_led.set_low().unwrap(); + gpiob.pb3.into_alternate_af0().set_speed(Speed::VeryHigh); + + logger::init(); + // Configure ethernet IO { let _rmii_refclk = gpioa.pa1.into_alternate_af11().set_speed(Speed::VeryHigh); @@ -254,9 +265,10 @@ fn main() -> ! { } match net_interface.poll_delay(&sockets, clock.elapsed()) { - Some(net::time::Duration {millis :0}) => debug!("resuming"), + Some(net::time::Duration {millis :0}) => { + continue; + } Some(time_delay) => { - info!("sleeping for {} ms", time_delay); // green_led.set_low().unwrap(); // delay.delay_ms(time_delay.total_millis() as u32); // green_led.set_high().unwrap(); diff --git a/examples/util/logger.rs b/examples/util/logger.rs index 155f6c8..c6ab530 100644 --- a/examples/util/logger.rs +++ b/examples/util/logger.rs @@ -26,7 +26,7 @@ pub unsafe fn enable_itm( *(0x5c00_4fb0 as *mut u32) = 0xC5ACCE55; // SWO CODR Register: Set SWO speed - *(0x5c00_3010 as *mut _) = 400 - 1; + *(0x5c00_3010 as *mut _) = 200; // SWO SPPR Register: // 1 = Manchester @@ -64,7 +64,7 @@ use cortex_m_log::{ lazy_static! { static ref LOGGER: Logger> = Logger { - level: LevelFilter::Debug, + level: LevelFilter::Trace, inner: unsafe { InterruptSync::new( ItmDest::new(cortex_m::Peripherals::steal().ITM) @@ -77,7 +77,7 @@ pub fn init() { cortex_m_log::log::init(&LOGGER).unwrap(); } -use panic_semihosting as _; +// use panic_semihosting as _; use cortex_m_log::printer::semihosting; use cortex_m_log::printer::semihosting::Semihosting; diff --git a/gdb_config/debug.gdb b/gdb_config/debug.gdb index f16f872..124aff9 100644 --- a/gdb_config/debug.gdb +++ b/gdb_config/debug.gdb @@ -12,7 +12,9 @@ break HardFault break rust_begin_unwind # print using semihosting, slow af -monitor arm semihosting enable +# monitor arm semihosting enable +monitor tpiu config internal itm.fifo uart off 400000000 +monitor itm port 0 on # flash the program to STM32 load diff --git a/gdb_config/openocd.gdb b/gdb_config/openocd.gdb index d367e99..5227171 100644 --- a/gdb_config/openocd.gdb +++ b/gdb_config/openocd.gdb @@ -12,9 +12,9 @@ break HardFault break rust_begin_unwind # print using semihosting, slow af -monitor arm semihosting enable -# monitor tpiu config internal itm.fifo uart off 400000000 -# monitor itm port 0 on +# monitor arm semihosting enable +monitor tpiu config internal itm.fifo uart off 400000000 +monitor itm port 0 on # flash the program to STM32 load