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migen: changed mosi

pull/4/head
occheung 2020-09-24 17:10:31 +08:00
parent 3211261488
commit d462f065a9
1 changed files with 8 additions and 3 deletions
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11
migen/fpga_config.py
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@ -10,6 +10,9 @@ from migen.genlib.io import *
class UrukulConnector(Module):
def __init__(self, platform):
# Include extension
spi_mosi = [
("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
]
spi_cs = [
("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
]
@ -20,6 +23,7 @@ class UrukulConnector(Module):
# Add extensions
platform.add_extension(spi_cs)
platform.add_extension(io_update)
platform.add_extension(spi_mosi)
# Request EEM I/O & SPI
eem0 = [
@ -34,12 +38,13 @@ class UrukulConnector(Module):
platform.request("eem0", 6)
]
spi = platform.request("spi")
spi_mosi = platform.request("spi_mosi")
spi_cs = platform.request("spi_cs")
led = platform.request("user_led")
io_update = platform.request("io_update")
assert len(spi.clk) == 1
assert len(spi.mosi) == 1
assert len(spi_mosi) == 1
assert len(spi.miso) == 1
assert len(spi_cs) == 3
assert len(io_update) == 1
@ -61,8 +66,8 @@ class UrukulConnector(Module):
eem0[0].p.eq(spi.clk),
eem0[0].n.eq(~spi.clk),
eem0[1].p.eq(spi.mosi),
eem0[1].n.eq(~spi.mosi),
eem0[1].p.eq(spi_mosi),
eem0[1].n.eq(~spi_mosi),
spi.miso.eq(~self.miso_n),