diff --git a/migen/fpga_config.py b/migen/fpga_config.py
index 0f613a2..8c980f1 100644
--- a/migen/fpga_config.py
+++ b/migen/fpga_config.py
@@ -4,7 +4,7 @@ from migen.fhdl.module import Module
 class UrukulConnector(Module):
 	def __init__(self, platform):
 		# Request EEM I/O & SPI
-		eem = platform.request("eem", 1)
+		eem = platform.request("eem", 0)
 		spi = platform.request("spi")
 
 		# Assert signal length