diff --git a/examples/fpga_config.rs b/examples/fpga_config.rs
index b050d87..91b72d3 100644
--- a/examples/fpga_config.rs
+++ b/examples/fpga_config.rs
@@ -3,20 +3,12 @@
 
 extern crate log;
 use log::debug;
-
-use stm32h7xx_hal::hal::digital::v2::{
-	InputPin,
-	OutputPin,
-};
-use stm32h7xx_hal::{gpio::Speed, pac, prelude::*, spi};
+use stm32h7xx_hal::{pac, prelude::*, spi};
 
 use cortex_m;
 use cortex_m::asm::nop;
 use cortex_m_rt::entry;
 
-use core::ptr;
-use nb::block;
-
 use firmware::flash::flash_ice40_fpga;
 
 #[path = "util/logger.rs"]
@@ -42,7 +34,7 @@ fn main() -> ! {
 		logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
 	}
 	
-	let mut delay = cp.SYST.delay(ccdr.clocks);
+	let delay = cp.SYST.delay(ccdr.clocks);
 
 	let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
 	let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
@@ -61,14 +53,14 @@ fn main() -> ! {
 	let fpga_sdi = gpiob.pb5.into_alternate_af5();
 
 	// Setup SPI_SS_B and CRESET_B
-	let mut fpga_ss = gpioa.pa4.into_push_pull_output();
-	let mut fpga_creset = gpiof.pf3.into_open_drain_output();
+	let fpga_ss = gpioa.pa4.into_push_pull_output();
+	let fpga_creset = gpiof.pf3.into_open_drain_output();
 
 	// Setup CDONE
 	let fpga_cdone = gpiod.pd15.into_pull_up_input();
 
 	// Setup SPI interface
-	let mut fpga_cfg_spi = dp.SPI1.spi(
+	let fpga_cfg_spi = dp.SPI1.spi(
 		(fpga_sck, fpga_sdo, fpga_sdi),
 		spi::MODE_3,
 		12.mhz(),
diff --git a/migen/fpga_config.py b/migen/fpga_config.py
index 20fb3d6..c4c7e82 100644
--- a/migen/fpga_config.py
+++ b/migen/fpga_config.py
@@ -1,24 +1,26 @@
 # Import built in I/O, Connectors & Platform template for Humpback
 from migen.build.platforms.sinara import humpback
-# Import migen platform for Lattice Products
-from migen.build.lattice import LatticePlatform
 # Import migen pin record structure
 from migen.build.generic_platform import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance
 from migen.genlib.io import *
-from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
-from migen.genlib.io import DifferentialInput
 
-spi_cs = [
-	("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
-]
-io_update = [
-	("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
-]
 
 class UrukulConnector(Module):
 	def __init__(self, platform):
+		# Include extension
+		spi_cs = [
+			("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
+		]
+		io_update = [
+			("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
+		]
+
+		# Add extensions
+		platform.add_extension(spi_cs)
+		platform.add_extension(io_update)
+
 		# Request EEM I/O & SPI
 		eem0 = [
 			platform.request("eem0", 0),
@@ -82,6 +84,4 @@ class UrukulConnector(Module):
 
 if __name__ == "__main__":
 	platform = humpback.Platform()
-	platform.add_extension(spi_cs)
-	platform.add_extension(io_update)
 	platform.build(UrukulConnector(platform))