From 9ec5698f63ff29a970c660fa957c9fad50395171 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 24 Aug 2020 10:57:37 +0800 Subject: [PATCH] migen: replace ethernet conflict pin --- .cargo/config | 2 +- migen/humpback.py | 4 +-- src/main.rs | 78 +++++++++++++++++++++++++++++++---------------- 3 files changed, 54 insertions(+), 30 deletions(-) diff --git a/.cargo/config b/.cargo/config index c0ce242..6c91033 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = "gdb -q -x gdb_config/fpga_config.gdb" +runner = "gdb -q -x gdb_config/debug.gdb" rustflags = [ "-C", "link-arg=-Tlink.x", ] diff --git a/migen/humpback.py b/migen/humpback.py index c31a76b..3d88bd9 100644 --- a/migen/humpback.py +++ b/migen/humpback.py @@ -33,10 +33,10 @@ _io.append( # Resource: DDS I/O_Update ''' - io_update -> PB13 : B12 + io_update -> PB15 : A11 ''' _io.append( - ("io_update", 0, Pins("B12"), IOStandard("LVCMOS33")) + ("io_update", 0, Pins("A11"), IOStandard("LVCMOS33")) ) # Inherit Platform to gain the programmed clock attribute diff --git a/src/main.rs b/src/main.rs index 31ecd9d..394eae1 100644 --- a/src/main.rs +++ b/src/main.rs @@ -73,9 +73,7 @@ fn main() -> ! { let sclk = gpioa.pa5.into_alternate_af5(); let mosi = gpiob.pb5.into_alternate_af5(); let miso = gpioa.pa6.into_alternate_af5(); -// let mut sclk = gpioa.pa5.into_push_pull_output(); -// let mut mosi = gpiob.pb5.into_push_pull_output(); -// let mut miso = gpioa.pa6.into_pull_up_input(); + let (mut cs0, mut cs1, mut cs2) = ( gpiob.pb12.into_push_pull_output(), @@ -83,6 +81,11 @@ fn main() -> ! { gpioc.pc7.into_push_pull_output(), ); + /* + * I/O_Update -> PB13 + */ + let mut io_update = gpiob.pb15.into_push_pull_output(); + let mut spi = dp.SPI1.spi( (sclk, miso, mosi), spi::MODE_0, @@ -94,13 +97,15 @@ fn main() -> ! { // debug led let mut yellow = gpioe.pe1.into_push_pull_output(); yellow.set_high().unwrap(); - + +/* let mut switch = CPLD::new(spi, (cs0, cs1, cs2)); let parts = switch.split(); let mut config = ConfigRegister::new(parts.spi1); let mut att = Attenuator::new(parts.spi2); let mut dds0 = DDS::new(parts.spi4); + loop { let mut counter = config.get_status(StatusMask::RF_SW).unwrap(); hprintln!("{}", counter); @@ -108,36 +113,55 @@ fn main() -> ! { (CFGMask::RF_SW, ((counter + 1)%16) as u32) ]).unwrap(); } +*/ -/* cs0.set_low().unwrap(); cs1.set_low().unwrap(); cs2.set_low().unwrap(); - cs2.set_high().unwrap(); - let mut arr: [u8; 5] = [0x00, 0x00, 0x00, 0x00, 0x02]; - hprintln!("Feedback of conf: {:?}", spi.transfer(&mut arr).unwrap()).unwrap(); - cs2.set_low().unwrap(); + io_update.set_low().unwrap(); - arr[0] = 0x80; - arr[1] = 0; - arr[2] = 0; - arr[3] = 0; - arr[4] = 0; - cs1.set_high().unwrap(); - hprintln!("first proper feedback: {:?}", spi.transfer(&mut arr).unwrap()).unwrap(); + let mut dummy :[u8;1] = [0]; + spi.transfer(&mut dummy); + + // Master reset DDS_0 through CPLD, with LED at 3 + cs0.set_high().unwrap(); + spi.transfer(&mut [ + 0x08, 0x00, 0x03 + ]).unwrap(); + cs0.set_low().unwrap(); + + // Perform I/O Reset through CPLD, with LED at 4 + cs0.set_high().unwrap(); + spi.transfer(&mut [ + 0x10, 0x00, 0x04 + ]).unwrap(); + cs0.set_low().unwrap(); + + // Release reset, control I/O Update through EEM + cs0.set_high().unwrap(); + spi.transfer(&mut [ + 0x00, 0x00, 0x0A + ]).unwrap(); + cs0.set_low().unwrap(); + + cs0.set_low().unwrap(); cs1.set_low().unwrap(); + cs2.set_high().unwrap(); + + hprintln!("{:?}", spi.transfer(&mut [ + 0x00, 0x00, 0x00, 0x00, 0x02 + ]).unwrap()).unwrap(); - loop { - arr[0] = 0x81; - arr[1] = 0; - arr[2] = 0; - arr[3] = 0; - arr[4] = 0; - cs1.set_high().unwrap(); - hprintln!("{:?}", spi.transfer(&mut arr).unwrap()).unwrap(); - cs1.set_low().unwrap(); - } -*/ + io_update.set_high().unwrap(); + delay.delay_ms(1_u16); + io_update.set_low().unwrap(); + + hprintln!("{:?}", spi.transfer(&mut [ + 0x80, 0x00, 0x00, 0x00, 0x00 + ]).unwrap()).unwrap(); + + + loop {} }