urukul: add urukul clock config getter

This commit is contained in:
occheung 2020-09-29 14:22:05 +08:00
parent 3abc0c3e4e
commit 95443a2283
1 changed files with 25 additions and 0 deletions

View File

@ -173,6 +173,18 @@ where
self.set_clock_division(division)
}
pub fn get_clock_source(&mut self) -> Result<ClockSource, Error<E>> {
match (
self.config_register.get_configuration(CFGMask::CLK_SEL0),
self.config_register.get_configuration(CFGMask::CLK_SEL1)
) {
(0, 0) => Ok(ClockSource::OSC),
(0, 1) => Ok(ClockSource::MMCX),
(1, _) => Ok(ClockSource::SMA),
_ => Err(Error::ConfigRegisterError)
}
}
pub fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
// Change clock source through configuration register
match source {
@ -190,6 +202,10 @@ where
}.map(|_| ())
}
pub fn get_clock_frequency(&mut self) -> f64 {
self.f_master_clk
}
pub fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
// Update master clock frequency
self.f_master_clk = frequency;
@ -198,6 +214,15 @@ where
self.set_dds_ref_clk()
}
pub fn get_clock_division(&mut self) -> Result<u8, Error<E>> {
match self.config_register.get_configuration(CFGMask::DIV) {
0| 3 => Ok(4),
1 => Ok(1),
2 => Ok(2),
_ => Err(Error::ConfigRegisterError)
}
}
pub fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
match division {
1 => self.config_register.set_configurations(&mut [