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migen: fix eem port

This commit is contained in:
occheung 2020-08-20 09:53:39 +08:00
parent 6e6e500f8a
commit 39d49b43c2
1 changed files with 17 additions and 3 deletions
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20
migen/fpga_config.py
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@ -6,6 +6,7 @@ class UrukulConnector(Module):
# Request EEM I/O & SPI # Request EEM I/O & SPI
eem = platform.request("eem", 0) eem = platform.request("eem", 0)
spi = platform.request("spi") spi = platform.request("spi")
led = platform.request("user_led")
# Assert signal length # Assert signal length
assert len(eem.p) == 8 assert len(eem.p) == 8
@ -15,21 +16,34 @@ class UrukulConnector(Module):
assert len(spi.miso) == 1 assert len(spi.miso) == 1
assert len(spi.cs) == 3 assert len(spi.cs) == 3
# Flip positive signal as negative output # Flip positive signal as negative output, maybe only do it for FPGA outputs
self.comb += eem.n.eq(~eem.p) # self.comb += eem.n.eq(~eem.p)
# Link EEM to SPI # Link EEM to SPI
self.comb += [ self.comb += [
eem.p[0].eq(spi.sclk), eem.p[0].eq(spi.sclk),
eem.n[0].eq(~spi.sclk),
eem.p[1].eq(spi.mosi), eem.p[1].eq(spi.mosi),
eem.n[1].eq(~spi.mosi),
spi.miso.eq(eem.p[2]), spi.miso.eq(eem.p[2]),
eem.p[3].eq(spi.cs[0]), eem.p[3].eq(spi.cs[0]),
eem.n[3].eq(~spi.cs[0]),
eem.p[4].eq(spi.cs[1]), eem.p[4].eq(spi.cs[1]),
eem.n[4].eq(~spi.cs[1]),
eem.p[5].eq(spi.cs[2]), eem.p[5].eq(spi.cs[2]),
eem.n[5].eq(~spi.cs[2]),
led.eq(1)
] ]
# Debug purposes: Tie EEM MISO to EEM MOSI # Debug purposes: Tie EEM MISO to EEM MOSI
self.comb += eem.p[2].eq(eem.p[1]) # self.comb += eem.p[2].eq(eem.p[1])
if __name__ == "__main__": if __name__ == "__main__":