diff --git a/migen/fpga_config.py b/migen/fpga_config.py
index 8c980f1..db4825d 100644
--- a/migen/fpga_config.py
+++ b/migen/fpga_config.py
@@ -6,6 +6,7 @@ class UrukulConnector(Module):
 		# Request EEM I/O & SPI
 		eem = platform.request("eem", 0)
 		spi = platform.request("spi")
+		led = platform.request("user_led")
 
 		# Assert signal length
 		assert len(eem.p) == 8
@@ -15,21 +16,34 @@ class UrukulConnector(Module):
 		assert len(spi.miso) == 1
 		assert len(spi.cs) == 3
 
-		# Flip positive signal as negative output
-		self.comb += eem.n.eq(~eem.p)
+		# Flip positive signal as negative output, maybe only do it for FPGA outputs
+		# self.comb += eem.n.eq(~eem.p)
 
 		# Link EEM to SPI
 		self.comb += [
+
 			eem.p[0].eq(spi.sclk),
+			eem.n[0].eq(~spi.sclk),
+
 			eem.p[1].eq(spi.mosi),
+			eem.n[1].eq(~spi.mosi),
+
 			spi.miso.eq(eem.p[2]),
+
 			eem.p[3].eq(spi.cs[0]),
+			eem.n[3].eq(~spi.cs[0]),
+
 			eem.p[4].eq(spi.cs[1]),
+			eem.n[4].eq(~spi.cs[1]),
+
 			eem.p[5].eq(spi.cs[2]),
+			eem.n[5].eq(~spi.cs[2]),
+
+			led.eq(1)
 		]
 
 		# Debug purposes: Tie EEM MISO to EEM MOSI
-		self.comb += eem.p[2].eq(eem.p[1])
+		# self.comb += eem.p[2].eq(eem.p[1])
 
 
 if __name__ == "__main__":