From 181ef5c72adf98a21099aec9d885465ee57cc3b3 Mon Sep 17 00:00:00 2001 From: occheung Date: Tue, 25 Aug 2020 12:20:24 +0800 Subject: [PATCH] attenuator: fix reverse data --- .cargo/config | 2 +- src/attenuator.rs | 58 ++++++++++++---------- src/main.rs | 124 ++++++++-------------------------------------- 3 files changed, 54 insertions(+), 130 deletions(-) diff --git a/.cargo/config b/.cargo/config index 6c91033..86b3292 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = "gdb -q -x gdb_config/debug.gdb" +runner = "gdb -q -x gdb_config/openocd.gdb" rustflags = [ "-C", "link-arg=-Tlink.x", ] diff --git a/src/attenuator.rs b/src/attenuator.rs index d2f05ac..3b90235 100644 --- a/src/attenuator.rs +++ b/src/attenuator.rs @@ -17,11 +17,16 @@ where pub fn new(spi: SPI) -> Self { Attenuator { spi, + // data[y] refers to the yth byte for SPI communication data: [0, 0, 0, 0], } } - pub fn set_attenuation(&mut self, att: [f32; 4]) -> Result<[u8; 4], Error> { + /* + * Set attenuations of all attenuators + * att[x] refers to the attenuation for channel x + */ + pub fn set_attenuation(&mut self, att: [f32; 4]) -> Result<(), Error> { for i in 0..4 { let mut atten = att[i]; if att[i] > 31.5 { @@ -30,48 +35,49 @@ where if att[i] < 0.0 { atten = 0.0; } - self.data[i] = (atten * 2.0) as u8; - self.data[i] = self.data[i] << 2; + // Set data as attenuation * 2 + // Flip data using bitwise XOR, active low data + // Data is most signifant attenuator first + self.data[3-i] = (((atten * 2.0) as u8) ^ 0xFF) << 2 } let mut clone = self.data.clone(); // Transmit SPI once to set attenuation - if self.spi.transfer(&mut clone).map_err(Error::SPI).is_err() { - return Err(Error::AttenuatorError); - } - - // Transmit the same data again, to get the return value - // Report the data returned by SPI, or an error - clone = self.data.clone(); match self.spi.transfer(&mut clone).map_err(Error::SPI) { - Ok(arr) => { - Ok([arr[0], arr[1], arr[2], arr[3]]) - }, - err => Err(Error::AttenuatorError) + Err(e) => Err(Error::AttenuatorError), + Ok(_) => Ok(()), } } - pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result> { + pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error> { assert!(channel < 4); - let mut arr: [f32; 4] = self.get_attenuation(); + let mut arr: [f32; 4] = self.get_attenuation()?; arr[channel as usize] = attenuation; match self.set_attenuation(arr) { - Ok(v) => Ok(v[channel as usize]), + Ok(v) => Ok(()), Err(e) => Err(e) } } - pub fn get_channel_attenuation(&mut self, channel: u8) -> f32 { + pub fn get_channel_attenuation(&mut self, channel: u8) -> Result> { assert!(channel < 4); - (self.data[channel as usize] as f32)/8.0 + match self.get_attenuation() { + Ok(arr) => Ok(arr[channel as usize]), + Err(e) => Err(e), + } } - pub fn get_attenuation(&mut self) -> [f32; 4] { - [ - self.get_channel_attenuation(0), - self.get_channel_attenuation(1), - self.get_channel_attenuation(2), - self.get_channel_attenuation(3), - ] + pub fn get_attenuation(&mut self) -> Result<[f32; 4], Error> { + let mut clone = self.data.clone(); + match self.spi.transfer(&mut clone).map_err(Error::SPI) { + Ok(arr) => { + let mut ret :[f32; 4] = [0.0; 4]; + for index in 0..4 { + ret[index] = ((arr[3 - index] ^ 0xFC) as f32) / 8.0; + } + Ok(ret) + }, + Err(e) => Err(e), + } } } diff --git a/src/main.rs b/src/main.rs index 3bde150..ddd11ba 100644 --- a/src/main.rs +++ b/src/main.rs @@ -84,8 +84,7 @@ fn main() -> ! { /* * I/O_Update -> PB13 */ - // TODO: Incoporate io_update into DDS - let mut io_update = gpiob.pb15.into_push_pull_output(); + let io_update = gpiob.pb15.into_push_pull_output(); let spi = dp.SPI1.spi( (sclk, miso, mosi), @@ -94,7 +93,7 @@ fn main() -> ! { ccdr.peripheral.SPI1, &ccdr.clocks, ); - + let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update); let parts = switch.split(); @@ -119,18 +118,10 @@ fn main() -> ! { 0x00, 0x00, 0x00, 0x02 ]).unwrap(); -// io_update.set_high().unwrap(); -// io_update.set_low().unwrap(); -// switch.issue_io_update(); - dds0.write_register(0x02, &mut[ - 0x01F, 0x3F, 0xC0, 0x00 + 0x01F, 0x3F, 0x41, 0x00 ]).unwrap(); -// io_update.set_high().unwrap(); -// io_update.set_low().unwrap(); -// switch.issue_io_update(); - hprintln!("{:#X?}", dds0.read_register(0x00, &mut[ 0x00, 0x00, 0x00, 0x00 ]).unwrap()).unwrap(); @@ -148,109 +139,36 @@ fn main() -> ! { dds0.read_register(0x0E, &mut profile).unwrap(); // Overwrite FTW on profile + profile[0] = 0x20; profile[4] = ((ftw >> 24) & 0xFF) as u8; profile[5] = ((ftw >> 16) & 0xFF) as u8; profile[6] = ((ftw >> 8 ) & 0xFF) as u8; profile[7] = ((ftw >> 0 ) & 0xFF) as u8; dds0.write_register(0x0E, &mut profile).unwrap(); -// io_update.set_high().unwrap(); -// io_update.set_low().unwrap(); -// switch.issue_io_update(); hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap(); - + + // Attenuator + att.set_attenuation([ + 0.0, 31.5, 24.0, 0.0 + ]).unwrap(); + + hprintln!("{:#X?}", att.get_attenuation().unwrap()).unwrap(); + /* - cs0.set_low().unwrap(); - cs1.set_low().unwrap(); - cs2.set_low().unwrap(); - - io_update.set_low().unwrap(); - - let mut dummy :[u8;1] = [0]; - spi.transfer(&mut dummy); - - // Master reset DDS_0 through CPLD, with LED at 3 - cs0.set_high().unwrap(); - spi.transfer(&mut [ - 0x08, 0x00, 0x03 - ]).unwrap(); - cs0.set_low().unwrap(); - - // Perform I/O Reset through CPLD, with LED at 4 - cs0.set_high().unwrap(); - spi.transfer(&mut [ - 0x10, 0x00, 0x04 - ]).unwrap(); - cs0.set_low().unwrap(); - - // Release reset, control I/O Update through EEM - // Relay clock signal from internal OSC (CLK_SEL = 0) - // Enable Switch 0 - cs0.set_high().unwrap(); - spi.transfer(&mut [ - 0x00, 0x00, 0x01 - ]).unwrap(); - cs0.set_low().unwrap(); - - cs0.set_low().unwrap(); - cs1.set_low().unwrap(); - cs2.set_high().unwrap(); - - // Configure SDIO to be input only, enable 3-wires communication - spi.transfer(&mut [ - 0x00, 0x00, 0x00, 0x00, 0x02 + // Write to FTW register + dds0.write_register(0x07, &mut [ + ((ftw >> 24) & 0xFF) as u8, + ((ftw >> 16) & 0xFF) as u8, + ((ftw >> 8 ) & 0xFF) as u8, + ((ftw >> 0 ) & 0xFF) as u8, ]).unwrap(); - // IO Update after every SPI transfer - io_update.set_high().unwrap(); - delay.delay_ms(1_u16); - io_update.set_low().unwrap(); - - // Bypass PLL, bypass divisor - spi.transfer(&mut [ - 0x02, 0x1F, 0x3F, 0xC0, 0x00 - ]).unwrap(); - - io_update.set_high().unwrap(); - delay.delay_ms(1_u16); - io_update.set_low().unwrap(); - - hprintln!("{:#X?}", spi.transfer(&mut [ - 0x82, 0x00, 0x00, 0x00, 0x00 + hprintln!("{:#X?}", dds0.read_register(0x07, &mut [ + 0x00, 0x00, 0x00, 0x00 ]).unwrap()).unwrap(); - - let f_out = 10_000_000.0; - let f_sclk = 100_000_000.0; - let resolution :u64 = 1 << 32; - let ftw = ((resolution as f32) * f_out / f_sclk) as u32; - hprintln!("{:#X}", ftw); - - // Read profile 0 - let mut profile_arr_0 :[u8; 9] = [0; 9]; - profile_arr_0[0] = 0x8E; - hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap(); - - // Write FTW to profile 0 - profile_arr_0[0] = 0x0E; - profile_arr_0[5] = ((ftw >> 24) & 0xFF) as u8; - profile_arr_0[6] = ((ftw >> 16) & 0xFF) as u8; - profile_arr_0[7] = ((ftw >> 8 ) & 0xFF) as u8; - profile_arr_0[8] = ((ftw >> 0 ) & 0xFF) as u8; - - hprintln!("{:#X?}", profile_arr_0).unwrap(); - spi.transfer(&mut profile_arr_0).unwrap(); - - // Update after write - io_update.set_high().unwrap(); - delay.delay_ms(1_u16); - io_update.set_low().unwrap(); - - // Read profile again, new value should be present - profile_arr_0[0] = 0x8E; - hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap(); -*/ - +*/ loop {} }