From 14aab2d0402fd1397b29ffd2398e5a6540933a31 Mon Sep 17 00:00:00 2001 From: occheung Date: Tue, 11 Aug 2020 08:54:00 +0800 Subject: [PATCH] nmigen: purged --- nmigen/fpga_config.py | 43 ------ nmigen/humpback.py | 339 ------------------------------------------ nmigen/resources.py | 90 ----------- shell.nix | 19 +-- 4 files changed, 8 insertions(+), 483 deletions(-) delete mode 100644 nmigen/fpga_config.py delete mode 100644 nmigen/humpback.py delete mode 100644 nmigen/resources.py diff --git a/nmigen/fpga_config.py b/nmigen/fpga_config.py deleted file mode 100644 index 158c86d..0000000 --- a/nmigen/fpga_config.py +++ /dev/null @@ -1,43 +0,0 @@ - -# If the design does not create a "sync" clock domain, it is created by the nMigen build system -# using the platform default clock (and default reset, if any). - -from nmigen import * -from humpback import * - - -#class SimpleBlinky(Elaboratable): -# def elaborate(self, platform): -# led = platform.request("user_led", 0) -# counter = Signal(24) -# m = Module() -# m.d.sync += counter.eq(counter + 1) -# m.d.comb += led.o.eq(counter[23]) -# return m - - -# Simple connector from STM32 SPI to Humpback SPI -class UrukulConnector(Elaboratable): - def elaborate(self, platform): - # Acquire SPI slave, EEM port 1 output - spi = platform.request("spi") - print(spi) - eem = platform.request("eem", 1) - print(eem) - clk25 = platform.request("clk25") - counter = Signal(25) - - m = Module() - m.domains.sync = ClockDomain() - m.d.comb += ClockSignal().eq(clk25.i) - m.d.sync += counter.eq(counter + 1) - return m - - - - -if __name__ == "__main__": - platform = HumpbackPlatform() - platform.add_resources(platform.eem_to_urukul) - platform.add_resources(platform.spi) - platform.build(UrukulConnector(), do_program=False) diff --git a/nmigen/humpback.py b/nmigen/humpback.py deleted file mode 100644 index 78ebdcf..0000000 --- a/nmigen/humpback.py +++ /dev/null @@ -1,339 +0,0 @@ -# Strongly inspired by the migen build of humpback -# Using STM32 Nucleo-H743ZI2 board -# Note to self: Pin assignment differs from Nucleo-H743ZI - -import os -import subprocess - -from nmigen.build import * -from nmigen.vendor.lattice_ice40 import * -from nmigen_boards.resources import * -from resources import * - - -__all__ = ["HumpbackPlatform"] - - -class HumpbackPlatform(LatticeICE40Platform): - device = "iCE40HX8K" # Using ICE40HX8K-CT256 - package = "CT256" - default_clk = "clk25" - - resources = [ - - # Define clock - Resource("clk25", 0, Pins("K9", dir="i"), - Clock(25e6), Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS") - ), - - # Define user LED - Resource("user_led", 0, Pins("H3", dir="o"), - Attrs(IO_STANDARD="SB_LVCMOS") - ), - - # TODO: Define UART interfaces somewhere else, make it optional - UARTResource(0, - rx="T11", tx="M13", rts="M15", cts="T10", - attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1) - ), - - # UART1 interface: Read note for UART interface above - # UART1 interface is broken due to pin rearrangement introduced for Nucleo-H743ZI2 - # Uncomment if fixed, or found an alternative (e.g. bit banging UART) -# *UARTResource(1, -# tx="M11", rx="T13", rts="A6", cts="B16", -# attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1) -# ), - - # Define I2C interface - # TODO: Make it optional, declare it in a block itself - # Use "role=device" to make humpback a I2C slave - I2CResource(0, - sda="T16", scl="M12", - attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1) - ), - ] - - # Using the dict approach in (o)migen - connectors = [ - - # EEM0 Connector - Connector("eem", 0, { - "d0_cc_n": "H1", - "d0_cc_p": "J3", - "d1_n" : "B1", - "d1_p" : "F5", - "d2_n" : "C2", - "d2_p" : "C1", - "d3_n" : "D2", - "d3_p" : "F4", - "d4_n" : "D1", - "d4_p" : "G5", - "d5_n" : "E3", - "d5_p" : "G4", - "d6_n" : "E2", - "d6_p" : "H5", - "d7_n" : "F3", - "d7_p" : "G3", - }), - - # EEM1 Connector - Connector("eem", 1, { - "d0_cc_n": "L3", - "d0_cc_p": "L6", - "d1_n" : "F1", - "d1_p" : "H6", - "d2_n" : "G2", - "d2_p" : "H4", - "d3_n" : "H2", - "d3_p" : "J4", - "d4_n" : "J1", - "d4_p" : "J2", - "d5_n" : "K3", - "d5_p" : "K1", - "d6_n" : "L1", - "d6_p" : "L4", - "d7_n" : "M1", - "d7_p" : "K4", - }), - - # EEM2 Connector - Connector("eem", 2, { - "d0_cc_n": "G1", - "d0_cc_p": "J5", - "d1_n" : "M2", - "d1_p" : "K5", - "d2_n" : "N2", - "d2_p" : "L7", - "d3_n" : "M3", - "d3_p" : "M6", - "d4_n" : "N3", - "d4_p" : "L5", - "d5_n" : "M4", - "d5_p" : "P1", - "d6_n" : "M5", - "d6_p" : "P2", - "d7_n" : "N4", - "d7_p" : "R1", - }), - - # STM32 Nucleo/ Arduino Connector - # TODO: Suspect SPI mismatch forever - Connector("stm32", 0, { - "PA0": "A2", -# "PA1": "P14", # PA1 -> PB2, but PB2 has a mapping on FPGA already -# "PA2": "B8", # PA2 -> PF6 - "PA3": "L13", - "PA5": "C8", - "PA6": "T2", -# "PA7": "N12", # PA7 -> PE9, but PE9 has a mapping on FPGA already -# "PA8": "M9", # PA8 -> PF2 -# "PA9": "P10", # PA9 -> PF1 -# "PA10": "R10", # PA10 -> PF0 - "PA15": "B14", - - "PB0": "A1", -# "PB1": "G12", # PB1 -> PF4 - "PB1": "M14", # PC1 -> PB1 - "PB2": "B6", - "PB5": "N5", -# "PB6": "A7", # PB6 -> PG6 - "PB6": "T13", # PG9 -> PB6 - "PB7": "M11", # PG10 -> PB7 - "PB8": "M12", - "PB9": "T16", - "PB10": "C3", - "PB11": "F7", - "PB12": "B13", - "PB13": "B12", - "PB15": "A11", - - "PC0": "L14", -# "PC1": "M14", # PC1 -> PB1 -# "PC2": "A9", # PC2 -> PF5 - "PC2": "N16", # PC4 -> PC2 - "PC3": "M16", -# "PC4": "N16", # PC4 -> PC2 -# "PC5": "P16", # PC5 -> PF10 - "PC6": "B10", - "PC7": "B15", - "PC8": "H16", - "PC9": "J10", - "PC10": "J16", - "PC11": "J15", - "PC12": "K12", - - "PD0": "T9", - "PD1": "N9", - "PD2": "K13", - "PD3": "T10", - "PD4": "A6", - "PD5": "T11", - "PD6": "M13", - "PD7": "L12", - "PD11": "E5", - "PD12": "D5", - "PD13": "C5", - "PD14": "R2", - - "PE0": "D3", - "PE2": "P15", - "PE3": "N10", - "PE4": "R15", - "PE5": "T15", - "PE6": "M8", - "PE7": "E6", - "PE8": "D6", - "PE9": "F12", - "PE10": "A5", - "PE11": "G11", - "PE12": "B4", -# "PE13": "F11", # PE13 -> PG12 -# "PE14": "C4", # PE14 -> PE6, but PE6 has a mapping on FPGA already - "PE14": "B9", # PF14 -> PE14 - "PE15": "B3", - - "PF0": "R10", # PA10 -> PF0 - "PF1": "P10", # PA9 -> PF1 - "PF2": "M9", # PA8 -> PF2 - "PF4": "G12", # PB1 -> PF4 - "PF5": "A9", # PC2 -> PF5 - "PF6": "B8", # PA2 -> PF6 - "PF7": "L9", - "PF8": "L10", - "PF9": "P9", - "PF10": "P16", # PC5 -> PF10 -# "PF14": "B9", # PF14 -> PE14 -# "PF15": "B16", # PF15 -> PG14 - - "PG0": "M7", - "PG1": "P8", - "PG2": "K14", - "PG3": "K15", - "PG6": "A7", # PB6 -> PG6 -# "PG9": "T13", # PG9 -> PB6 -# "PG10": "M11", # PG10 -> PB7 - "PG12": "F11", # PE13 -> PG12 - "PG14": "B16", # PF15 -> PG14 - }), - - # Beaglebone Black Connector - Connector("bb", 0, { - "CLKOUT": "R9", - - "GPIO0_7": "R14", - - "GPIO1_16": "A16", - "GPIO1_17": "R3", - "GPIO1_29": "D11", - "GPIO1_31": "D14", - - "GPIO2_6": "D16", - "GPIO2_7": "C16", - "GPIO2_8": "E16", - "GPIO2_9": "D15", - "GPIO2_11": "F15", - "GPIO2_13": "F16", - "GPIO2_22": "C11", - "GPIO2_23": "C10", - "GPIO2_24": "E10", - "GPIO2_25": "D4", - - "GPIO3_19": "P4", - "GPIO3_21": "R4", - - "GPMC_A2": "T7", - "GPMC_A3": "T1", - "GPMC_A14": "F9", - "GPMC_A15": "B7", - "GPMC_AD0": "C12", - "GPMC_AD1": "E11", - "GPMC_AD2": "J12", - "GPMC_AD3": "J11", - "GPMC_AD4": "C13", - "GPMC_AD5": "C14", - "GPMC_AD6": "J14", - "GPMC_AD7": "J13", - "GPMC_AD8": "E13", - "GPMC_AD9": "G13", - "GPMC_AD10": "G14", - "GPMC_AD11": "G10", - "GPMC_AD12": "E14", - "GPMC_AD13": "H14", - "GPMC_AD14": "F14", - "GPMC_AD15": "F13", - "GPMC_ADVN": "H12", - "GPMC_BE0N": "G16", - "GPMC_CLK": "H11", - "GPMC_CSN1": "D13", - "GPMC_OEN": "H13", - "GPMC_WE1N": "G15", - }), - - # ESP32 Connector - Connector("esp32", 0, { - "IO2": "D9", - "IO4": "D7", - "IO22": "C7", - "IO34": "E9", - "IO35": "C9", - }), - - # OrangePI Zero Connector - Connector("orange_pi", 0, { - "PG06": "A15", - }), - ] - - - # Half completed, second EEM resource to be added - # Appears that DiffPairs cause build problem -# eem_to_urukul_diffpairs = [ -# Resource("eem", 1, -# Subsignal("sclk", DiffPairs("L6", "L3", dir="o")), -# Subsignal("mosi", DiffPairs("H6", "F1", dir="o")), -# Subsignal("miso", DiffPairs("H4", "G2", dir="i"), -# Attrs(IO_STANDARD="SB_LVDS_INPUT")), -# Subsignal("cs", DiffPairs("K1 J2 J4", "K3 J1 H2", dir="o")), -# Subsignal("io_update", DiffPairs("L4", "L1", dir="o")), -# Subsignal("sync_out", DiffPairs("K4", "M1", dir="o")), -# Attrs(IO_STANDARD="SB_LVCMOS") -# ) -# ] - - eem_to_urukul = [ - Resource("eem", 1, - Subsignal("sclk_p", Pins("L6", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("sclk_n", Pins("L3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), -# Subsignal("sclk", DiffPairs("L6", "L3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("mosi_p", Pins("H6", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("mosi_n", Pins("F1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), -# Subsignal("miso_p", Pins("H4", dir="i"), Attrs(IO_STANDARD="SB_IDK")), -# Subsignal("miso_n", Pins("G2", dir="i"), Attrs(IO_STANDARD="SB_LOL")), - Subsignal("miso", DiffPairs("H4", "G2", dir="i"), Attrs(IO_STANDARD="SB_LVDS_INPUT")), - Subsignal("cs_p", Pins("J4 J2 K1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("cs_n", Pins("H2 J1 K3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("io_update_p", Pins("L4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("io_update_n", Pins("L1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("sync_out_p", Pins("K4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - Subsignal("sync_out_n", Pins("M1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), - ), - ] - - # SPI Connection to Urukul, using (PD14, PA15, PC7) as connection pins - spi = [ - Resource("spi", 0, - Subsignal("cs", Pins("R2 B14 B15", dir="i")), - Subsignal("mosi", Pins("N5", dir="i")), - Subsignal("miso", Pins("T2", dir="oe")), - Subsignal("sck", Pins("C8", dir="i"), - Attrs(GLOBAL=True)), - Attrs(IO_STANDARD="SB_LVCMOS") - ) - ] - - # tool chain setup, using default ICE40 HX8K evaluation code - def toolchain_program(self, products, name): - iceprog = os.environ.get("ICEPROG", "iceprog") - with products.extract("{}.bin".format(name)) as bitstream_filename: - subprocess.check_call([iceprog, "-S", bitstream_filename]) diff --git a/nmigen/resources.py b/nmigen/resources.py deleted file mode 100644 index d3da795..0000000 --- a/nmigen/resources.py +++ /dev/null @@ -1,90 +0,0 @@ -from nmigen.build import * - - -__all__ = ["I2CResource"] - - -def I2CResource(*args, sda, scl, conn=None, attrs=None, role="host"): - assert role in ("host", "device") - - io = [] - - # sda line: I/O port for the data line - io.append(Subsignal("sda", Pins(sda, dir="io", conn=conn, assert_width=1))) - - # sck line: I2C clock signal outputs from master to slave - if role == "host": - io.append(Subsignal("scl", Pins(scl, dir="o", conn=conn, assert_width=1))) - else: #device - io.append(Subsignal("scl", Pins(scl, dir="i", conn=conn, assert_width=1))) - - if attrs is not None: - io.append(attrs) - return Resource.family(*args, default_name="i2c", ios=io) - -''' -# Auto create a resource list given a set of iCE40 pins and STM32 pin names (pins_dict) -def GPIOResources(*args, pins_dict, dir = "o", invert=False, conn=None, attrs=None): - - # Check data integrity: pins_dict must be a dict AND port must be from a to k - assert isinstance(pins_dict, dict) - - # Debug: dir == "o" - assert dir == "o" - - # List of resources to be returned - resources = [] - for STM32_pin, iCE40_pin in pins_dict.items(): - - # Set all gpio pins to be output only for the time being - - # TODO: Allow dir argument. - ios = [Pins(iCE40_pin, dir=dir, invert=invert, conn=conn)] - if attrs is not None: - ios.append(attrs) - - # Extract GPIO port and port number from STM32_pin - # Strip "P" from P - if STM32_pin.startswith('P'): - STM32_pin = STM32_pin[1:] - - # Acquire port from - port = STM32_pin[0].lower() - port_num = int(STM32_pin[1:]) - - # Insert gpio. into resources list - resources.append(Resource.family(*args, port_num, default_name=("gpio"+port), ios=ios)) - return resources - -# Auto create a resource list for differential I/O -def DiffResources(*args, eem_pins, invert=False, conn=None, attrs=None, dir): - # TODO: Everything - - # assert dimensionality - assert isinstance(eem_pins, list) - assert isinstance(eem_pins[0], list) - assert isinstance(eem_pins[0][0], list) - assert isinstance(eem_pins[0][0][0], str) - - # assert direction to be either input or output - # reject tristate or bidirectional pin - assert dir in ("i", "o") - - - - -if __name__ == "__main__": - - from pin_mapper import * - eem = diffMapping() - DiffResources(eem_pins = eem, dir = "o", - attrs=Attrs(IO_STANDARD="SB_LVCMOS") - ) -''' - - - - - - - diff --git a/shell.nix b/shell.nix index f319c42..91b2954 100644 --- a/shell.nix +++ b/shell.nix @@ -4,9 +4,6 @@ let in with pkgs; let migen = callPackage ./nix/migen.nix {}; - # nMigen support for DiffPairs and IO_STANDARD="SB_LVDS_INPUT" seems questionable - nmigen = callPackage ./nix/nmigen.nix {}; - nmigen-boards = callPackage ./nix/nmigen-boards.nix { inherit nmigen; }; openocd = callPackage ./nix/openocd.nix {}; rustPlatform = callPackage ./nix/rustPlatform.nix {}; itm = callPackage ./nix/itm.nix {inherit rustPlatform;}; @@ -37,12 +34,12 @@ let set-gdb-config-file && cargo run --example ethernet ''; - editNMigenScript = writeShellScriptBin "edit-nmigen-script" '' - nano -m nmigen/fpga_config.py + editMigenScript = writeShellScriptBin "edit-migen-script" '' + nano -m migen/fpga_config.py ''; - compileNMigenScript = writeShellScriptBin "compile-nmigen-script" '' - python3 nmigen/fpga_config.py + compileMigenScript = writeShellScriptBin "compile-migen-script" '' + python3 migen/fpga_config.py echo "Compiled fpga_config.py to top.bin" ''; @@ -52,7 +49,7 @@ let configureFPGA = writeShellScriptBin "configure-fpga" '' nc -zv localhost 3333 \ - && compile-nmigen-script \ + && compile-migen-script \ && flash-fpga-config \ || echo "Please run OpenOcd first." ''; @@ -72,7 +69,7 @@ in stdenv.mkDerivation { name = "nix-shell"; buildInputs = with rustPlatform.rust; [ - (pkgs.python3.withPackages(ps: [ migen nmigen nmigen-boards])) + (pkgs.python3.withPackages(ps: [ migen ])) pkgs.yosys pkgs.nextpnr pkgs.icestorm @@ -85,8 +82,8 @@ in runOpenOcdBlock setGDBConfigFile runEthernetServer - editNMigenScript - compileNMigenScript + editMigenScript + compileMigenScript flashFPGAConfig configureFPGA verifyFPGAConfig