master
Jorge Aparicio 2017-04-10 11:29:31 -05:00
parent bce5fb5a6e
commit a88ea4011b
1 changed files with 280 additions and 234 deletions

514
build.rs
View File

@ -78,7 +78,7 @@ mod c {
} }
/// Compile intrinsics from the compiler-rt C source code /// Compile intrinsics from the compiler-rt C source code
pub fn compile(llvm_target: &[&str]){ pub fn compile(llvm_target: &[&str]) {
let target_arch = env::var("CARGO_CFG_TARGET_ARCH").unwrap(); let target_arch = env::var("CARGO_CFG_TARGET_ARCH").unwrap();
let target_env = env::var("CARGO_CFG_TARGET_ENV").unwrap(); let target_env = env::var("CARGO_CFG_TARGET_ENV").unwrap();
let target_os = env::var("CARGO_CFG_TARGET_OS").unwrap(); let target_os = env::var("CARGO_CFG_TARGET_OS").unwrap();
@ -102,9 +102,9 @@ mod c {
cfg.define("VISIBILITY_HIDDEN", None); cfg.define("VISIBILITY_HIDDEN", None);
} }
// NOTE Most of the ARM intrinsics are written in assembly. Tell gcc which arch we are going to // NOTE Most of the ARM intrinsics are written in assembly. Tell gcc which arch we are going
// target to make sure that the assembly implementations really work for the target. If the // to target to make sure that the assembly implementations really work for the target. If
// implementation is not valid for the arch, then gcc will error when compiling it. // the implementation is not valid for the arch, then gcc will error when compiling it.
if llvm_target[0].starts_with("thumb") { if llvm_target[0].starts_with("thumb") {
cfg.flag("-mthumb"); cfg.flag("-mthumb");
@ -126,112 +126,130 @@ mod c {
} }
let mut sources = Sources::new(); let mut sources = Sources::new();
sources.extend(&["absvdi2.c", sources.extend(
"absvsi2.c", &[
"addvdi3.c", "absvdi2.c",
"addvsi3.c", "absvsi2.c",
"apple_versioning.c", "addvdi3.c",
"clzdi2.c", "addvsi3.c",
"clzsi2.c", "apple_versioning.c",
"cmpdi2.c", "clzdi2.c",
"comparedf2.c", "clzsi2.c",
"comparesf2.c", "cmpdi2.c",
"ctzdi2.c", "comparedf2.c",
"ctzsi2.c", "comparesf2.c",
"divdc3.c", "ctzdi2.c",
"divdf3.c", "ctzsi2.c",
"divsc3.c", "divdc3.c",
"divsf3.c", "divdf3.c",
"divxc3.c", "divsc3.c",
"extendsfdf2.c", "divsf3.c",
"extendhfsf2.c", "divxc3.c",
"ffsdi2.c", "extendsfdf2.c",
"fixdfdi.c", "extendhfsf2.c",
"fixdfsi.c", "ffsdi2.c",
"fixsfdi.c", "fixdfdi.c",
"fixsfsi.c", "fixdfsi.c",
"fixunsdfdi.c", "fixsfdi.c",
"fixunsdfsi.c", "fixsfsi.c",
"fixunssfdi.c", "fixunsdfdi.c",
"fixunssfsi.c", "fixunsdfsi.c",
"fixunsxfdi.c", "fixunssfdi.c",
"fixunsxfsi.c", "fixunssfsi.c",
"fixxfdi.c", "fixunsxfdi.c",
"floatdidf.c", "fixunsxfsi.c",
"floatdisf.c", "fixxfdi.c",
"floatdixf.c", "floatdidf.c",
"floatsidf.c", "floatdisf.c",
"floatsisf.c", "floatdixf.c",
"floatundidf.c", "floatsidf.c",
"floatundisf.c", "floatsisf.c",
"floatundixf.c", "floatundidf.c",
"floatunsidf.c", "floatundisf.c",
"floatunsisf.c", "floatundixf.c",
"int_util.c", "floatunsidf.c",
"muldc3.c", "floatunsisf.c",
"muldf3.c", "int_util.c",
"mulsc3.c", "muldc3.c",
"mulsf3.c", "muldf3.c",
"mulvdi3.c", "mulsc3.c",
"mulvsi3.c", "mulsf3.c",
"mulxc3.c", "mulvdi3.c",
"negdf2.c", "mulvsi3.c",
"negdi2.c", "mulxc3.c",
"negsf2.c", "negdf2.c",
"negvdi2.c", "negdi2.c",
"negvsi2.c", "negsf2.c",
"paritydi2.c", "negvdi2.c",
"paritysi2.c", "negvsi2.c",
"popcountdi2.c", "paritydi2.c",
"popcountsi2.c", "paritysi2.c",
"powixf2.c", "popcountdi2.c",
"subvdi3.c", "popcountsi2.c",
"subvsi3.c", "powixf2.c",
"truncdfhf2.c", "subvdi3.c",
"truncdfsf2.c", "subvsi3.c",
"truncsfhf2.c", "truncdfhf2.c",
"ucmpdi2.c"]); "truncdfsf2.c",
"truncsfhf2.c",
"ucmpdi2.c",
],
);
if target_os != "ios" { if target_os != "ios" {
sources.extend(&["absvti2.c", sources.extend(
"addvti3.c", &[
"clzti2.c", "absvti2.c",
"cmpti2.c", "addvti3.c",
"ctzti2.c", "clzti2.c",
"ffsti2.c", "cmpti2.c",
"fixdfti.c", "ctzti2.c",
"fixsfti.c", "ffsti2.c",
"fixunsdfti.c", "fixdfti.c",
"fixunssfti.c", "fixsfti.c",
"fixunsxfti.c", "fixunsdfti.c",
"fixxfti.c", "fixunssfti.c",
"floattidf.c", "fixunsxfti.c",
"floattisf.c", "fixxfti.c",
"floattixf.c", "floattidf.c",
"floatuntidf.c", "floattisf.c",
"floatuntisf.c", "floattixf.c",
"floatuntixf.c", "floatuntidf.c",
"mulvti3.c", "floatuntisf.c",
"negti2.c", "floatuntixf.c",
"negvti2.c", "mulvti3.c",
"parityti2.c", "negti2.c",
"popcountti2.c", "negvti2.c",
"subvti3.c", "parityti2.c",
"ucmpti2.c"]); "popcountti2.c",
"subvti3.c",
"ucmpti2.c",
],
);
} }
if target_vendor == "apple" { if target_vendor == "apple" {
sources.extend(&["atomic_flag_clear.c", sources.extend(
"atomic_flag_clear_explicit.c", &[
"atomic_flag_test_and_set.c", "atomic_flag_clear.c",
"atomic_flag_test_and_set_explicit.c", "atomic_flag_clear_explicit.c",
"atomic_signal_fence.c", "atomic_flag_test_and_set.c",
"atomic_thread_fence.c"]); "atomic_flag_test_and_set_explicit.c",
"atomic_signal_fence.c",
"atomic_thread_fence.c",
],
);
} }
if target_env == "msvc" { if target_env == "msvc" {
if target_arch == "x86_64" { if target_arch == "x86_64" {
sources.extend(&["x86_64/floatdidf.c", "x86_64/floatdisf.c", "x86_64/floatdixf.c"]); sources.extend(
&[
"x86_64/floatdidf.c",
"x86_64/floatdisf.c",
"x86_64/floatdixf.c",
],
);
} }
} else { } else {
if target_os != "freebsd" && target_os != "netbsd" { if target_os != "freebsd" && target_os != "netbsd" {
@ -239,120 +257,140 @@ mod c {
} }
if target_arch == "x86_64" { if target_arch == "x86_64" {
sources.extend(&["x86_64/chkstk.S", sources.extend(
"x86_64/chkstk2.S", &[
"x86_64/floatdidf.c", "x86_64/chkstk.S",
"x86_64/floatdisf.c", "x86_64/chkstk2.S",
"x86_64/floatdixf.c", "x86_64/floatdidf.c",
"x86_64/floatundidf.S", "x86_64/floatdisf.c",
"x86_64/floatundisf.S", "x86_64/floatdixf.c",
"x86_64/floatundixf.S"]); "x86_64/floatundidf.S",
"x86_64/floatundisf.S",
"x86_64/floatundixf.S",
],
);
} }
if target_arch == "x86" { if target_arch == "x86" {
sources.extend(&["i386/ashldi3.S", sources.extend(
"i386/ashrdi3.S", &[
"i386/chkstk.S", "i386/ashldi3.S",
"i386/chkstk2.S", "i386/ashrdi3.S",
"i386/divdi3.S", "i386/chkstk.S",
"i386/floatdidf.S", "i386/chkstk2.S",
"i386/floatdisf.S", "i386/divdi3.S",
"i386/floatdixf.S", "i386/floatdidf.S",
"i386/floatundidf.S", "i386/floatdisf.S",
"i386/floatundisf.S", "i386/floatdixf.S",
"i386/floatundixf.S", "i386/floatundidf.S",
"i386/lshrdi3.S", "i386/floatundisf.S",
"i386/moddi3.S", "i386/floatundixf.S",
"i386/muldi3.S", "i386/lshrdi3.S",
"i386/udivdi3.S", "i386/moddi3.S",
"i386/umoddi3.S"]); "i386/muldi3.S",
"i386/udivdi3.S",
"i386/umoddi3.S",
],
);
} }
} }
if target_arch == "arm" && target_os != "ios" { if target_arch == "arm" && target_os != "ios" {
sources.extend(&["arm/aeabi_cdcmp.S", sources.extend(
"arm/aeabi_cdcmpeq_check_nan.c", &[
"arm/aeabi_cfcmp.S", "arm/aeabi_cdcmp.S",
"arm/aeabi_cfcmpeq_check_nan.c", "arm/aeabi_cdcmpeq_check_nan.c",
"arm/aeabi_dcmp.S", "arm/aeabi_cfcmp.S",
"arm/aeabi_div0.c", "arm/aeabi_cfcmpeq_check_nan.c",
"arm/aeabi_drsub.c", "arm/aeabi_dcmp.S",
"arm/aeabi_fcmp.S", "arm/aeabi_div0.c",
"arm/aeabi_frsub.c", "arm/aeabi_drsub.c",
"arm/bswapdi2.S", "arm/aeabi_fcmp.S",
"arm/bswapsi2.S", "arm/aeabi_frsub.c",
"arm/clzdi2.S", "arm/bswapdi2.S",
"arm/clzsi2.S", "arm/bswapsi2.S",
"arm/comparesf2.S", "arm/clzdi2.S",
"arm/divmodsi4.S", "arm/clzsi2.S",
"arm/divsi3.S", "arm/comparesf2.S",
"arm/modsi3.S", "arm/divmodsi4.S",
"arm/switch16.S", "arm/divsi3.S",
"arm/switch32.S", "arm/modsi3.S",
"arm/switch8.S", "arm/switch16.S",
"arm/switchu8.S", "arm/switch32.S",
"arm/sync_synchronize.S", "arm/switch8.S",
"arm/udivmodsi4.S", "arm/switchu8.S",
"arm/udivsi3.S", "arm/sync_synchronize.S",
"arm/umodsi3.S"]); "arm/udivmodsi4.S",
"arm/udivsi3.S",
"arm/umodsi3.S",
],
);
} }
if llvm_target[0] == "armv7" { if llvm_target[0] == "armv7" {
sources.extend(&["arm/sync_fetch_and_add_4.S", sources.extend(
"arm/sync_fetch_and_add_8.S", &[
"arm/sync_fetch_and_and_4.S", "arm/sync_fetch_and_add_4.S",
"arm/sync_fetch_and_and_8.S", "arm/sync_fetch_and_add_8.S",
"arm/sync_fetch_and_max_4.S", "arm/sync_fetch_and_and_4.S",
"arm/sync_fetch_and_max_8.S", "arm/sync_fetch_and_and_8.S",
"arm/sync_fetch_and_min_4.S", "arm/sync_fetch_and_max_4.S",
"arm/sync_fetch_and_min_8.S", "arm/sync_fetch_and_max_8.S",
"arm/sync_fetch_and_nand_4.S", "arm/sync_fetch_and_min_4.S",
"arm/sync_fetch_and_nand_8.S", "arm/sync_fetch_and_min_8.S",
"arm/sync_fetch_and_or_4.S", "arm/sync_fetch_and_nand_4.S",
"arm/sync_fetch_and_or_8.S", "arm/sync_fetch_and_nand_8.S",
"arm/sync_fetch_and_sub_4.S", "arm/sync_fetch_and_or_4.S",
"arm/sync_fetch_and_sub_8.S", "arm/sync_fetch_and_or_8.S",
"arm/sync_fetch_and_umax_4.S", "arm/sync_fetch_and_sub_4.S",
"arm/sync_fetch_and_umax_8.S", "arm/sync_fetch_and_sub_8.S",
"arm/sync_fetch_and_umin_4.S", "arm/sync_fetch_and_umax_4.S",
"arm/sync_fetch_and_umin_8.S", "arm/sync_fetch_and_umax_8.S",
"arm/sync_fetch_and_xor_4.S", "arm/sync_fetch_and_umin_4.S",
"arm/sync_fetch_and_xor_8.S"]); "arm/sync_fetch_and_umin_8.S",
"arm/sync_fetch_and_xor_4.S",
"arm/sync_fetch_and_xor_8.S",
],
);
} }
if llvm_target.last().unwrap().ends_with("eabihf") { if llvm_target.last().unwrap().ends_with("eabihf") {
if !llvm_target[0].starts_with("thumbv7em") { if !llvm_target[0].starts_with("thumbv7em") {
sources.extend(&["arm/adddf3vfp.S", sources.extend(
"arm/addsf3vfp.S", &[
"arm/divdf3vfp.S", "arm/adddf3vfp.S",
"arm/divsf3vfp.S", "arm/addsf3vfp.S",
"arm/eqdf2vfp.S", "arm/divdf3vfp.S",
"arm/eqsf2vfp.S", "arm/divsf3vfp.S",
"arm/extendsfdf2vfp.S", "arm/eqdf2vfp.S",
"arm/fixdfsivfp.S", "arm/eqsf2vfp.S",
"arm/fixsfsivfp.S", "arm/extendsfdf2vfp.S",
"arm/fixunsdfsivfp.S", "arm/fixdfsivfp.S",
"arm/fixunssfsivfp.S", "arm/fixsfsivfp.S",
"arm/floatsidfvfp.S", "arm/fixunsdfsivfp.S",
"arm/floatsisfvfp.S", "arm/fixunssfsivfp.S",
"arm/floatunssidfvfp.S", "arm/floatsidfvfp.S",
"arm/floatunssisfvfp.S", "arm/floatsisfvfp.S",
"arm/gedf2vfp.S", "arm/floatunssidfvfp.S",
"arm/gesf2vfp.S", "arm/floatunssisfvfp.S",
"arm/gtdf2vfp.S", "arm/gedf2vfp.S",
"arm/gtsf2vfp.S", "arm/gesf2vfp.S",
"arm/ledf2vfp.S", "arm/gtdf2vfp.S",
"arm/lesf2vfp.S", "arm/gtsf2vfp.S",
"arm/ltdf2vfp.S", "arm/ledf2vfp.S",
"arm/ltsf2vfp.S", "arm/lesf2vfp.S",
"arm/muldf3vfp.S", "arm/ltdf2vfp.S",
"arm/mulsf3vfp.S", "arm/ltsf2vfp.S",
"arm/nedf2vfp.S", "arm/muldf3vfp.S",
"arm/nesf2vfp.S", "arm/mulsf3vfp.S",
"arm/restore_vfp_d8_d15_regs.S", "arm/nedf2vfp.S",
"arm/save_vfp_d8_d15_regs.S", "arm/nesf2vfp.S",
"arm/subdf3vfp.S", "arm/restore_vfp_d8_d15_regs.S",
"arm/subsf3vfp.S"]); "arm/save_vfp_d8_d15_regs.S",
"arm/subdf3vfp.S",
"arm/subsf3vfp.S",
],
);
} }
sources.extend(&["arm/negdf2vfp.S", "arm/negsf2vfp.S"]); sources.extend(&["arm/negdf2vfp.S", "arm/negsf2vfp.S"]);
@ -360,43 +398,51 @@ mod c {
} }
if target_arch == "aarch64" { if target_arch == "aarch64" {
sources.extend(&["comparetf2.c", sources.extend(
"extenddftf2.c", &[
"extendsftf2.c", "comparetf2.c",
"fixtfdi.c", "extenddftf2.c",
"fixtfsi.c", "extendsftf2.c",
"fixtfti.c", "fixtfdi.c",
"fixunstfdi.c", "fixtfsi.c",
"fixunstfsi.c", "fixtfti.c",
"fixunstfti.c", "fixunstfdi.c",
"floatditf.c", "fixunstfsi.c",
"floatsitf.c", "fixunstfti.c",
"floatunditf.c", "floatditf.c",
"floatunsitf.c", "floatsitf.c",
"multc3.c", "floatunditf.c",
"trunctfdf2.c", "floatunsitf.c",
"trunctfsf2.c"]); "multc3.c",
"trunctfdf2.c",
"trunctfsf2.c",
],
);
} }
// Remove the assembly implementations that won't compile for the target // Remove the assembly implementations that won't compile for the target
if llvm_target[0] == "thumbv6m" { if llvm_target[0] == "thumbv6m" {
sources.remove(&["aeabi_cdcmp", sources.remove(
"aeabi_cfcmp", &[
"aeabi_dcmp", "aeabi_cdcmp",
"aeabi_fcmp", "aeabi_cfcmp",
"clzdi2", "aeabi_dcmp",
"clzsi2", "aeabi_fcmp",
"comparesf2", "clzdi2",
"divmodsi4", "clzsi2",
"divsi3", "comparesf2",
"modsi3", "divmodsi4",
"switch16", "divsi3",
"switch32", "modsi3",
"switch8", "switch16",
"switchu8", "switch32",
"udivmodsi4", "switch8",
"udivsi3", "switchu8",
"umodsi3"]); "udivmodsi4",
"udivsi3",
"umodsi3",
],
);
// But use some generic implementations where possible // But use some generic implementations where possible
sources.extend(&["clzdi2.c", "clzsi2.c"]) sources.extend(&["clzdi2.c", "clzsi2.c"])