From 6dcbd85f11f2a4b2ee47228a6288f90f83b8d883 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Thu, 26 Jul 2018 19:30:26 +0200
Subject: [PATCH] Implement __mulsi3.

---
 src/lib.rs     |  3 +++
 src/riscv32.rs | 17 +++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 src/riscv32.rs

diff --git a/src/lib.rs b/src/lib.rs
index 02b6c7d..9f1dd15 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -58,6 +58,9 @@ pub mod arm;
 #[cfg(all(kernel_user_helpers, target_os = "linux", target_arch = "arm"))]
 pub mod arm_linux;
 
+#[cfg(any(target_arch = "riscv32"))]
+pub mod riscv32;
+
 #[cfg(target_arch = "x86")]
 pub mod x86;
 
diff --git a/src/riscv32.rs b/src/riscv32.rs
new file mode 100644
index 0000000..ebaa354
--- /dev/null
+++ b/src/riscv32.rs
@@ -0,0 +1,17 @@
+intrinsics! {
+    // Implementation from gcc
+    // https://raw.githubusercontent.com/gcc-mirror/gcc/master/libgcc/config/epiphany/mulsi3.c
+    pub extern "C" fn __mulsi3(mut a: u32, mut b: u32) -> u32 {
+        let mut r: usize = 0;
+
+        while a > 0 {
+            if a & 1 > 0 {
+                r += b;
+            }
+            a >>= 1;
+            b <<= 1;
+        }
+
+        r
+    }
+}