Merge pull request #276 from hug-dev/armv8m-support
Fix compilation errors for Armv8-M Baseline and Mainline with FPU
This commit is contained in:
commit
4078c99f9b
39
build.rs
39
build.rs
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@ -50,10 +50,11 @@ fn main() {
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println!("cargo:rustc-cfg=thumb")
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println!("cargo:rustc-cfg=thumb")
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}
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}
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// compiler-rt `cfg`s away some intrinsics for thumbv6m because that target doesn't have full
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// compiler-rt `cfg`s away some intrinsics for thumbv6m and thumbv8m.base because
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// THUMBv2 support. We have to cfg our code accordingly.
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// these targets do not have full Thumb-2 support but only original Thumb-1.
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if llvm_target[0] == "thumbv6m" {
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// We have to cfg our code accordingly.
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println!("cargo:rustc-cfg=thumbv6m")
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if llvm_target[0] == "thumbv6m" || llvm_target[0] == "thumbv8m.base" {
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println!("cargo:rustc-cfg=thumb_1")
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}
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}
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// Only emit the ARM Linux atomic emulation on pre-ARMv6 architectures.
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// Only emit the ARM Linux atomic emulation on pre-ARMv6 architectures.
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@ -360,24 +361,36 @@ mod c {
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}
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}
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if llvm_target.last().unwrap().ends_with("eabihf") {
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if llvm_target.last().unwrap().ends_with("eabihf") {
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if !llvm_target[0].starts_with("thumbv7em") {
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if !llvm_target[0].starts_with("thumbv7em") &&
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!llvm_target[0].starts_with("thumbv8m.main") {
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// The FPU option chosen for these architectures in cc-rs, ie:
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// -mfpu=fpv4-sp-d16 for thumbv7em
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// -mfpu=fpv5-sp-d16 for thumbv8m.main
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// do not support double precision floating points conversions so the files
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// that include such instructions are not included for these targets.
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sources.extend(
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sources.extend(
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&[
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&[
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"arm/fixdfsivfp.S",
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"arm/fixdfsivfp.S",
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"arm/fixsfsivfp.S",
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"arm/fixunsdfsivfp.S",
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"arm/fixunsdfsivfp.S",
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"arm/fixunssfsivfp.S",
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"arm/floatsidfvfp.S",
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"arm/floatsidfvfp.S",
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"arm/floatsisfvfp.S",
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"arm/floatunssidfvfp.S",
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"arm/floatunssidfvfp.S",
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"arm/floatunssisfvfp.S",
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"arm/restore_vfp_d8_d15_regs.S",
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"arm/save_vfp_d8_d15_regs.S",
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],
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],
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);
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);
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}
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}
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sources.extend(&["arm/negdf2vfp.S", "arm/negsf2vfp.S"]);
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sources.extend(
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&[
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"arm/fixsfsivfp.S",
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"arm/fixunssfsivfp.S",
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"arm/floatsisfvfp.S",
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"arm/floatunssisfvfp.S",
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"arm/floatunssisfvfp.S",
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"arm/restore_vfp_d8_d15_regs.S",
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"arm/save_vfp_d8_d15_regs.S",
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"arm/negdf2vfp.S",
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"arm/negsf2vfp.S",
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]
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);
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}
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}
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@ -408,7 +421,7 @@ mod c {
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}
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}
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// Remove the assembly implementations that won't compile for the target
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// Remove the assembly implementations that won't compile for the target
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if llvm_target[0] == "thumbv6m" {
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if llvm_target[0] == "thumbv6m" || llvm_target[0] == "thumbv8m.base" {
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sources.remove(
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sources.remove(
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&[
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&[
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"clzdi2",
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"clzdi2",
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@ -19,9 +19,6 @@ extern crate panic_handler;
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#[link(name = "c")]
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#[link(name = "c")]
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extern {}
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extern {}
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// NOTE cfg(not(thumbv6m)) means that the operation is not supported on ARMv6-M at all. Not even
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// compiler-rt provides a C/assembly implementation.
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// Every function in this module maps will be lowered to an intrinsic by LLVM, if the platform
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// Every function in this module maps will be lowered to an intrinsic by LLVM, if the platform
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// doesn't have native support for the operation used in the function. ARM has a naming convention
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// doesn't have native support for the operation used in the function. ARM has a naming convention
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// convention for its intrinsics that's different from other architectures; that's why some function
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// convention for its intrinsics that's different from other architectures; that's why some function
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@ -39,70 +36,40 @@ mod intrinsics {
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}
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}
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// fixdfdi
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// fixdfdi
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#[cfg(not(thumbv6m))]
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pub fn aeabi_d2l(x: f64) -> i64 {
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pub fn aeabi_d2l(x: f64) -> i64 {
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x as i64
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x as i64
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_d2l(_: f64) -> i64 {
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0
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}
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// fixunsdfsi
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// fixunsdfsi
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pub fn aeabi_d2uiz(x: f64) -> u32 {
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pub fn aeabi_d2uiz(x: f64) -> u32 {
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x as u32
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x as u32
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}
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}
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// fixunsdfdi
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// fixunsdfdi
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#[cfg(not(thumbv6m))]
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pub fn aeabi_d2ulz(x: f64) -> u64 {
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pub fn aeabi_d2ulz(x: f64) -> u64 {
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x as u64
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x as u64
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_d2ulz(_: f64) -> u64 {
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0
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}
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// adddf3
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// adddf3
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pub fn aeabi_dadd(a: f64, b: f64) -> f64 {
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pub fn aeabi_dadd(a: f64, b: f64) -> f64 {
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a + b
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a + b
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}
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}
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// eqdf2
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// eqdf2
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#[cfg(not(thumbv6m))]
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pub fn aeabi_dcmpeq(a: f64, b: f64) -> bool {
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pub fn aeabi_dcmpeq(a: f64, b: f64) -> bool {
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a == b
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a == b
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_dcmpeq(_: f64, _: f64) -> bool {
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true
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}
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// gtdf2
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// gtdf2
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#[cfg(not(thumbv6m))]
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pub fn aeabi_dcmpgt(a: f64, b: f64) -> bool {
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pub fn aeabi_dcmpgt(a: f64, b: f64) -> bool {
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a > b
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a > b
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_dcmpgt(_: f64, _: f64) -> bool {
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true
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}
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// ltdf2
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// ltdf2
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#[cfg(not(thumbv6m))]
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pub fn aeabi_dcmplt(a: f64, b: f64) -> bool {
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pub fn aeabi_dcmplt(a: f64, b: f64) -> bool {
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a < b
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a < b
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_dcmplt(_: f64, _: f64) -> bool {
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true
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}
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// divdf3
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// divdf3
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pub fn aeabi_ddiv(a: f64, b: f64) -> f64 {
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pub fn aeabi_ddiv(a: f64, b: f64) -> f64 {
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a / b
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a / b
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@ -129,70 +96,40 @@ mod intrinsics {
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}
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}
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// fixsfdi
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// fixsfdi
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#[cfg(not(thumbv6m))]
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pub fn aeabi_f2lz(x: f32) -> i64 {
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pub fn aeabi_f2lz(x: f32) -> i64 {
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x as i64
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x as i64
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_f2lz(_: f32) -> i64 {
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0
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}
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// fixunssfsi
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// fixunssfsi
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pub fn aeabi_f2uiz(x: f32) -> u32 {
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pub fn aeabi_f2uiz(x: f32) -> u32 {
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x as u32
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x as u32
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}
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}
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// fixunssfdi
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// fixunssfdi
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#[cfg(not(thumbv6m))]
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pub fn aeabi_f2ulz(x: f32) -> u64 {
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pub fn aeabi_f2ulz(x: f32) -> u64 {
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x as u64
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x as u64
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_f2ulz(_: f32) -> u64 {
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0
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}
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// addsf3
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// addsf3
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pub fn aeabi_fadd(a: f32, b: f32) -> f32 {
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pub fn aeabi_fadd(a: f32, b: f32) -> f32 {
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a + b
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a + b
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}
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}
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// eqsf2
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// eqsf2
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#[cfg(not(thumbv6m))]
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pub fn aeabi_fcmpeq(a: f32, b: f32) -> bool {
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pub fn aeabi_fcmpeq(a: f32, b: f32) -> bool {
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a == b
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a == b
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_fcmpeq(_: f32, _: f32) -> bool {
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true
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}
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// gtsf2
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// gtsf2
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#[cfg(not(thumbv6m))]
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pub fn aeabi_fcmpgt(a: f32, b: f32) -> bool {
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pub fn aeabi_fcmpgt(a: f32, b: f32) -> bool {
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a > b
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a > b
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_fcmpgt(_: f32, _: f32) -> bool {
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true
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}
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// ltsf2
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// ltsf2
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#[cfg(not(thumbv6m))]
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pub fn aeabi_fcmplt(a: f32, b: f32) -> bool {
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pub fn aeabi_fcmplt(a: f32, b: f32) -> bool {
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a < b
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a < b
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}
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}
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#[cfg(thumbv6m)]
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pub fn aeabi_fcmplt(_: f32, _: f32) -> bool {
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true
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}
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// divsf3
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// divsf3
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pub fn aeabi_fdiv(a: f32, b: f32) -> f32 {
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pub fn aeabi_fdiv(a: f32, b: f32) -> f32 {
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a / b
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a / b
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@ -74,8 +74,8 @@ intrinsics! {
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#[use_c_shim_if(all(target_arch = "arm",
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#[use_c_shim_if(all(target_arch = "arm",
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not(target_os = "ios"),
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not(target_os = "ios"),
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not(target_env = "msvc")),
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not(target_env = "msvc"),
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not(thumbv6m))]
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not(thumb_1)))]
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pub extern "C" fn __modsi3(a: i32, b: i32) -> i32 {
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pub extern "C" fn __modsi3(a: i32, b: i32) -> i32 {
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a.mod_(b)
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a.mod_(b)
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}
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}
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@ -91,7 +91,7 @@ intrinsics! {
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}
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}
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#[use_c_shim_if(all(target_arch = "arm", not(target_env = "msvc"),
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#[use_c_shim_if(all(target_arch = "arm", not(target_env = "msvc"),
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not(target_os = "ios"), not(thumbv6m)))]
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not(target_os = "ios"), not(thumb_1)))]
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pub extern "C" fn __divmodsi4(a: i32, b: i32, rem: &mut i32) -> i32 {
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pub extern "C" fn __divmodsi4(a: i32, b: i32, rem: &mut i32) -> i32 {
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a.divmod(b, rem, |a, b| __divsi3(a, b))
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a.divmod(b, rem, |a, b| __divsi3(a, b))
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}
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}
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@ -212,7 +212,7 @@ intrinsics! {
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#[use_c_shim_if(all(target_arch = "arm",
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#[use_c_shim_if(all(target_arch = "arm",
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not(target_os = "ios"),
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not(target_os = "ios"),
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not(target_env = "msvc"),
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not(target_env = "msvc"),
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not(thumbv6m)))]
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not(thumb_1)))]
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/// Returns `n % d`
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/// Returns `n % d`
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pub extern "C" fn __umodsi3(n: u32, d: u32) -> u32 {
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pub extern "C" fn __umodsi3(n: u32, d: u32) -> u32 {
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let q = __udivsi3(n, d);
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let q = __udivsi3(n, d);
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@ -222,7 +222,7 @@ intrinsics! {
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#[use_c_shim_if(all(target_arch = "arm",
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#[use_c_shim_if(all(target_arch = "arm",
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not(target_os = "ios"),
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not(target_os = "ios"),
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not(target_env = "msvc"),
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not(target_env = "msvc"),
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not(thumbv6m)))]
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not(thumb_1)))]
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/// Returns `n / d` and sets `*rem = n % d`
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/// Returns `n / d` and sets `*rem = n % d`
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pub extern "C" fn __udivmodsi4(n: u32, d: u32, rem: Option<&mut u32>) -> u32 {
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pub extern "C" fn __udivmodsi4(n: u32, d: u32, rem: Option<&mut u32>) -> u32 {
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let q = __udivsi3(n, d);
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let q = __udivsi3(n, d);
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